參數(shù)資料
型號: i960 VH
廠商: Intel Corp.
英文描述: Embedded-PCI Processor(嵌入式PCI處理器)
中文描述: 嵌入式PCI處理器(嵌入式處理器的PCI)
文件頁數(shù): 19/64頁
文件大?。?/td> 851K
代理商: I960 VH
80960VH
Preliminary
Datasheet
19
W/R#
O
R(0)
H(Z)
P(Q)
WRITE/READ
specifies during a
T
cycle whether the operation is a write or
read. It is latched on-chip and remains valid during T
d
cycles.
0 = Read
1 = Write
WIDTH/
HLTD0
I/O
R(H)
H(Z)
P(Q)
WIDTH
denotes the physical memory attributes for a bus transaction in
conjunction with WIDTH/HLTD1/RETRY:
WIDTH/HLTD1/RETRY WIDTH/HLTD0
0
0
0
1
1
0
1
1
WIDTH/HLTD0 For proper operation, do not connect this signal to ground.
This signal has a weak internal pullup which is active during reset to ensure
normal operation.
HLTD0
signal name has no function in the 80960VH; the signal name is
included for 80960JT naming convention compatibility.
8 Bits Wide
16 Bits Wide
32 Bits Wide
Undefined
WIDTH/
HLTD1/
RETRY
I/O
R(H)
H(Z)
P(Q)
WIDTH
denotes the physical memory attributes for a bus transaction in
conjunction with the WIDTH/HLTD0 signal. Refer to description above.
RETRY
is sampled at primary PCI bus reset to determine when the primary
PCI interface is disabled. When high, the Primary PCI interface disables PCI
configuration cycles by signaling a RETRY until the Reset/Retry Control
Register’s Configuration Cycle Disable bit is cleared. When low, the primary
PCI interface allows configuration cycles to occur. WIDTH/HLTD1/RETRY
has a weak internal pullup which is active during reset to ensure normal
operation when the signal is not connected. When the RST_MODE# pin is
asserted, RETRY is internally forced low [inactive] regardless of its external
state.
HLTD1
signal name has no function in the 80960VH; the signal name is
included for 80960JT naming convention compatibility.
Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet 1 of 2)
NAME
TYPE
DESCRIPTION
FAIL#
O
R(0)
H(Q)
FAIL
indicates a failure of the processor’s built-in self-test performed
during initialization. FAIL# is asserted immediately upon reset and toggles
during self-test to indicate the status of individual tests:
When self-test passes, the processor deasserts FAIL# and
commences operation from user code.
When self-test fails, the processor asserts FAIL# and then stops
executing.
0 = Self Test Failed
1 = Self Test Passed
L_RST#
O
LOCAL BUS RESET
notifies external devices that the local bus has reset.
TCK
I
TEST CLOCK
is a CPU input that provides the clocking function for
IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data
are clocked into the processor on the rising edge; data is clocked out of the
processor on the falling edge.
TDI
I
S(L)
TEST DATA INPUT
is the serial input signal for JTAG. TDI is sampled on
the rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of the
Test Access Port. This signal has a weak internal pullup to ensure normal
operation.
Table 4. Signal Descriptions (Sheet 4 of 4)
NAME
TYPE
DESCRIPTION
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