參數(shù)資料
型號(hào)： i960 VH
廠商： Intel Corp.
英文描述： Embedded-PCI Processor(嵌入式PCI處理器)
中文描述： 嵌入式PCI處理器（嵌入式處理器的PCI）
文件頁(yè)數(shù)： 10/64頁(yè)
文件大小： 851K
代理商： I960 VH
80960VH
10
Preliminary Datasheet
2.2
i960
Core Features (80960JT)
The processing power of the 80960VH comes from the 80960JT processor core. The 80960JT is a
new, scalar implementation of the 80960 Core Architecture.
Figure
shows a block diagram of the
80960JT Core
processor.
Factors that contribute to the 80960 family core’s performance include:
Single-clock execution of most instructions
Independent Multiply/Divide Unit
Efficient instruction pipeline minimizes pipeline break latency
Register and resource scoreboarding allow overlapped instruction execution
128-bit register bus speeds local register caching
16 Kbyte two-way set-associative, integrated instruction cache
4 Kbyte direct-mapped, integrated data cache
1 Kbyte integrated data RAM delivers zero wait state program data
The 80960 core operates out of its own 32-bit address space, which is independent of the PCI
address space. The local bus memory can be:
Made visible to the PCI address space
Kept private to the 80960 core
Allocated as a combination of the two
Figure 2. 80960JT Core Block Diagram
Programmable
Interrupt Controller
CoBus
Control
Address/
Data Bus
Instruction Sequencer
Physical Region
Configuration
Interrupt
Port
1 K byte
Data RAM
Memory
Interface
Unit
Execution
and
Multiply
Divide
Unit
Memory-Mapped
Register Interface
Global / Local
Register File
SRC2
DST
SRC1
Address
Control
Effective
Constants
Generation
Unit
Address
32-bit Addr
32-bit Data
Bus Request
Queues
Two 32-Bit
Timers
8-Set
Local Register
Cache
S
S
D
PLL, Clocks,
Power Mgmt
Boundary Scan
Controller
TAP
5
128
S
S
D
S
D
9
32
32-bit buses
address / data
3 Independent 32-Bit SRC1, SRC2, and DST Buses
Instruction Cache
16 Kbyte Two-Way Set
4 Kbyte
Direct Mapped
Data Cache
P_CLK
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