參數(shù)資料
型號(hào)： i960 VH
廠商： Intel Corp.
英文描述： Embedded-PCI Processor(嵌入式PCI處理器)
中文描述： 嵌入式PCI處理器（嵌入式處理器的PCI）
文件頁(yè)數(shù)： 18/64頁(yè)
文件大?。?/td> 851K
代理商： I960 VH
80960VH
18
Preliminary Datasheet
LOCK#/ONCE#
I/O
S(L)
R(H)
H(Z)
P(Q)
BUS LOCK
indicates that an atomic read-modify-write operation is in
progress. The LOCK# output is asserted in the first clock of an atomic
operation and deasserted in the last data transfer of the sequence. The
processor does not grant HOLDA while asserting LOCK#. This prevents
external agents from accessing memory involved in semaphore operations.
0 = Atomic Read-Modify-Write in Progress
1 = No Atomic Read-Modify-Write in Progress
ONCE MODE:
The processor samples the ONCE input during reset. When
ONCE# is asserted LOW at the end of reset, the processor enters ONCE
mode, stops all clocks and floats all output signals. This signal has a weak
internal pullup which is active during reset to ensure normal operation when
the signal is not connected.
0 = ONCE Mode Enabled
1 = ONCE Mode Not Enabled
LRDYRCV#/
STEST
I/O
R(H)
H(Q)
P(Q)
LOCAL READY/RECOVER
, generated by the 80960VH
’s memory controller
unit, is an output version of the READY/RECOVER (RDYRCV#) signal. Refer
to the RDYRCV# signal description.
SELF TEST
enables or disables the processor’s internal self-test feature at
initialization. STEST is examined at the end of P_RST#. When STEST is
asserted, the processor performs its internal self-test and the external bus
confidence test. When STEST is deasserted, the processor performs only the
external bus confidence test. This signal has a weak internal pullup which is
active during reset to ensure normal operation.
0 = Self Test Disabled
1 = Self Test Enabled
HOLD
I
S(L)
HOLD
is a request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it asserts
HOLDA, floats the address/data and control lines and enters the T
h
state.
When HOLD is deasserted, the processor deasserts HOLDA and enters
either the T
i
or
T
state, resuming control of the address/data and control
lines. See
Figure , (pg. 61)
.
0 = No Hold Request
1 = Hold Requested
HOLDA
O
R(0)
H(1)
P(Q)
HOLD ACKNOWLEDGE
indicates to an external bus master that the
processor has relinquished bus control. The processor can grant HOLD
requests and enter the T
state and while halted as well as during regular
operation. See
Figure , (pg. 61)
.
0 = No Hold Acknowledged
1 = Hold Acknowledged
RDYRCV#
I
S(L)
READY/RECOVER
is only used in systems that use an external memory
controller (and do not use the 80960VH’s memory controller unit). This signal
indicates that data on AD lines can be sampled or removed. When RDYRCV#
is not asserted during a T
d
cycle, the T
d
cycle extends to the next cycle by
inserting a wait state (T
w
).
0 = Sample Data
1 = Do Not Sample Data
RDYRCV# has an alternate function during the recovery (T
) state. The
processor continues to insert recovery states until it samples the signal HIGH.
This gives slow external devices more time to float their buffers before the
processor drives addresses.
0 = Insert Wait States
1 = Recovery Complete
When using the internal memory controller, connect this signal to V
CC
through
a 2.7 K
resistor.
Table 4. Signal Descriptions (Sheet 3 of 4)
NAME
TYPE
DESCRIPTION
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