參數(shù)資料
型號： i960 VH
廠商： Intel Corp.
英文描述： Embedded-PCI Processor(嵌入式PCI處理器)
中文描述： 嵌入式PCI處理器（嵌入式處理器的PCI）
文件頁數(shù)： 21/64頁
文件大?。?/td> 851K
代理商： I960 VH
80960VH
Preliminary
Datasheet
21
Table 6. Interrupt Unit Signal Descriptions
NAME
TYPE
DESCRIPTION
NMI#
I
A(L)
NON-MASKABLE INTERRUPT
causes a non-maskable interrupt event to
occur. NMI# is the highest priority interrupt source and is level-detect. When
NMI# is unused, it is recommended that you connect it to V
CC
.
XINT3:0#
I
A(L)
EXTERNAL INTERRUPT
. External devices use this signal to request an
interrupt service. These signals operate in dedicated mode, where each signal
is assigned a dedicated interrupt level.
The XINT3:0# signals can be directed as follows:
External Int.
Primary PCI
XINT0#
P_INTA#
or
XINT1#
P_INTB#
or
XINT2#
P_INTC#
or
XINT3#
P_INTD#
or
80960 Core Processor
XINT0#
XINT1#
XINT2#
XINT3#
XINT7:4#
I
A(L)
EXTERNAL INTERRUPT
. External devices use this signal to request an
interrupt service. These signals operate in dedicated mode, where each signal
is assigned a dedicated interrupt level.
NOTE:
1.
PCI signal functions are summarized in this data sheet. Refer to the
PCI Local Bus Specification revision 2.2
for
a more complete definition.
Table 7. PCI Signal Descriptions (Sheet 1 of 2)
NAME
TYPE
DESCRIPTION
1
P_AD31:0
I/O
K(Q)
R(Z)
PRIMARY PCI ADDRESS/DATA
is the primary multiplexed PCI address and
data bus.
P_C/BE3:0#
I/O
K(Q)
R(Z)
PRIMARY PCI BUS COMMAND
and
BYTE ENABLE
signals
are multiplexed
on the same PCI signals. During an address phase, P_C/BE3:0# define the
bus command. During a data phase, P_C/BE3:0# are used as byte enables.
P_DEVSEL#
I/O
R(Z)
PRIMARY PCI BUS DEVICE SELECT
is driven by a target agent that has
successfully decoded the address. As an input, it indicates whether or not an
agent has been selected.
P_FRAME#
I/O
R(Z)
PRIMARY PCI BUS CYCLE FRAME
is asserted to indicate the beginning
and duration of an access on the Primary PCI bus.
P_GNT#
I
R(Z)
PRIMARY PCI BUS GRANT
indicates to the agent that access to the bus has
been granted. This is a point-to-point signal.
P_IDSEL
I
S(L)
PRIMARY PCI BUS INITIALIZATION DEVICE SELECT
selects the 80960VH
during a Configuration Read or Write command on the primary PCI bus.
P_INT[A:D]#
O
OD
R(Z)
PRIMARY PCI BUS INTERRUPT
requests an interrupt. The assertion and
deassertion of P_INTx# is asynchronous to
P_CLK
. A device asserts its
P_INTx# line when requesting attention from its device driver. Once the
P_INTx# signal is asserted, it remains asserted until the device driver clears
the pending request. P_INTx# Interrupts are level sensitive.
P_IRDY#
I/O
R(Z)
PRIMARY PCI BUS INITIATOR READY
indicates the initiating agent’s (bus
master’s) ability to complete the current data phase of the transaction.
NOTE:
1.
PCI signal functions are summarized in this data sheet; refer to the
PCI Local Bus Specification revision 2.2
for
a more complete definition.
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