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HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
9
Table 2.62 MCR Bit Definition..................................................................................103
Table 2.63 Autoflow Control Configuration.............................................................103
Table 2.64 LSR Bit Definition ...................................................................................104
Table 2.65 MSR Bit Definition ..................................................................................105
Table 2.66 DLL Bit Definition...................................................................................106
Table 2.67 DLM Bit Definition..................................................................................107
Table 2.68 Registers for TIMER...............................................................................108
Table 2.69 Clock Selection Register Bit Definition.................................................109
Table 2.70 Timer Control Register Bit Definition ...................................................110
Table 2.71 Timer Interval Register Bit Definition...................................................110
Table 2.72 Current Timer Value Register Bit Definition ........................................111
Table 2.73 Interrupt Source Register Bit Definition................................................111
Table 2.74 Interrupt Enable......................................................................................112
Table 2.75 Registers for GPIO..................................................................................113
Table 2.76 GPO Data Register Bit Definition...........................................................114
Table 2.77 GPI Data Register Bit Definition............................................................114
Table 2.78 GPIO Direction Register Bit Definition..................................................115
Table 2.79 Interrupt Source Register Bit Definition................................................115
Table 2.80 The Bit Definition of the Interrupt Enable Register .............................116
Table 2.81 Interrupt Mode Register Bit Definition..................................................116
Table 2.82 Interrupt Level Register Bit Definition..................................................116
Table 2.89 Registers for SPI.....................................................................................119
Table 2.90 SPI Control Register Bit Definition........................................................120
Table 2.91 Configuration Register Bit Definition ....................................................120
Table 2.92 Tx Data Register Bit Definition .............................................................121
Table 2.93 Rx Data Register Bit Definition..............................................................121
Table 2.94 Interrupt Source Register Bit Definition................................................121
Table 2.95 Interrupt Mask Register Bit Definition ..................................................122
Table 2.96 SPI Status Register Bit Definition..........................................................122
Table 2.97 DMA Initial Source Register...................................................................123
Table 2.98 DMA Initial Destination Register ...........................................................124
Table 2.99 DMA Control Register ............................................................................124
Table 2.100 DMA Status Register ............................................................................125