參數資料
型號: HMS30C7202
廠商: HYNIX SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-bit ARM7TDMI RISC static CMOS CPU core
中文描述: 32-BIT, 82.944 MHz, RISC PROCESSOR, PBGA256
封裝: 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-256
文件頁數: 133/161頁
文件大?。?/td> 973K
代理商: HMS30C7202
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
133
24
Reserved
16
Reserved
8
Reserved
0
INT_EXT0
2.12.1.2.
MODE REGISTER (INTMOD, offset = 0x04)
This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit
is set to 1, the corresponding interrupt is processed as the NMI request. Otherwise, it is processed as
a normal IRQ.
Note that at most only one interrupt source can be serviced in the NMI mode. (You should use the
NMI mode only for the urgent interrupt.) Thus, only one bit of INTMOD can be set to 1 at most.
This register is write-only one, thus it cannot be read out.
Table 2.98 Interrupt Mode Register
Address :
1930_0004
Register
Address
R/W
Description
Reset value
INTMOD 0x04
W
0 = IRQ mode, 1 = NMI mode
0x00000000
Each field and the corresponding bit position are the same as those of SRCPND register.
2.12.1.3.
INTERRUPT MASK REGISTER (INTMSK, offset = 0x08)
Each of the 32 bits in the interrupt mask register is related to an interrupt source. If you set a
specific bit to 1, the interrupt request from corresponding interrupt source is not serviced by CPU.
(Note that even in such a case, the corresponding bit of SRCPND register is set to 1). If the mask bit
is 0, the interrupt request can be serviced.
Table 2.99 Interrupt Mask Register
Address :
1930_0008
Register
Address
R/W
Description
Reset value
INTMSK 0x08
R/W
0 = Interrupt service is available
0xffffffff
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