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參數(shù)資料
| 型號(hào)： | HMS30C7202 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-bit ARM7TDMI RISC static CMOS CPU core |
| 中文描述： | 32-BIT, 82.944 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-256 |
| 文件頁(yè)數(shù)： | 132/161頁(yè) |
| 文件大?。?/td> | 973K |
| 代理商： | HMS30C7202 |
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HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
132
set to 1 if the corresponding interrupt source generates the interrupt request and waits for the
interrupt to be serviced. By reading this register, we can see the interrupt sources waiting for their
requests to be serviced. Note that each bit of SRCPND register is automatically set by the interrupt
sources regardless of the masking bits in the INTMASK register. In addition, it is not affected by
the priority logic of interrupt controller.
In the interrupt service routine for a specific interrupt source, the corresponding bit of SRCPND
register has to be cleared to get the interrupt request from the same source correctly. If you return
from the ISR (interrupt service routine) without clearing the bit, interrupt controller operates as if
another interrupt request comes in from the same source. In other words, if a specific bit of
SRCPND register is set to 1, it is always considered as a valid interrupt request waiting to be
serviced.
The specific time to clear the corresponding bit depends on the user's requirement. The bottom line
is that if you want to receive another valid request from the same source you should clear the
corresponding bit first, and then enable the interrupt.
You can clear a specific bit of SRCPND register by writing a data to this register. It clears only the
bit positions of SRCPND corresponding to those set to one in the data. The bit positions
corresponding to those that are set to 0 in the data remains as they are with no change.
Table 2.97 Source Pending Register
Address :
1930_0000
Register
Address
R/W
Description
value
SRCPND 0x00
R/W
0 = The interrupt has not been requested
1 = The interrupt source has asserted the interrupt
request
0x00000000
Bit
Field
Bit
Field
Bit
Field
Bit
Field
31
Reserved
23
Reserved
15
Reserved
7
INT_EXT7
30
Reserved
22
INT_CARDBUS
14
INT_ENET1
6
INT_EXT6
29
INT_UART1
21
INT_PCMIRQ
13
Reserved
5
INT_EXT5
28
INT_UART0
20
INT_PCMCIA
12
Reserved
4
INT_EXT4
27
INT_SPI
Reserved
19
INT_GPIO
11
INT_ENET0
3
INT_EXT3
26
18
INT_DMA1
10
INT_TIMER
2
INT_EXT2
25
Reserved
17
INT_DMA0
9
Reserved
1
INT_EXT1
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| HMS3224M3-12 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
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