參數(shù)資料
型號： HMS30C7202
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-bit ARM7TDMI RISC static CMOS CPU core
中文描述： 32-BIT, 82.944 MHz, RISC PROCESSOR, PBGA256
封裝： 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-256
文件頁數(shù)： 67/161頁
文件大?。?/td> 973K
代理商： HMS30C7202
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
67
2.6.
Ethernet MAC
HMS30C7110 provides an Ethernet Media Access Controller (MAC) that operates at either 10
Mbps or 100 Mbps in half-duplex or full-duplex mode. In half-duplex mode, the controller supports
the IEEE 802.3 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) protocol. It
supports the IEEE 802.3 MAC control layer, including the pause operation for flow control for full-
duplex mode.
The Ethernet MAC layer supports both Media Independent Interface (MII) / Reduced MII (RMII)
and 7-wire interface. The host side supports DMA interface to the system bus. The MAC layer itself
consists of the Receive and the Transmit blocks, a flow control block, multiple network address
storage, and a number of commands, and status registers.
The Transmit and Receive clocks will be supplied either from Physical layer devices or external
clock sources. They are either 2.5MHz at the 10 Mbps or 25MHz at the 100 Mbps. The external
clock for RMII is 50MHz regardless of data rate. The MII conforms to the ISO/IEC 802-3 standard
for a media-independent layer which separates physical layer issues form the MAC layer.
It also provides MAC address filtering, which is to drop frames with designated
MAC addresses while all other frames are received.
2.6.1.
Block Diagram
HMS30C7110 Ethernet MAC module consists of several sub-modules such as MII management,
physical layer interface, Receive, Transmit, Control, and Host Interface. Frames come in via either
7-wire interface (bit-wide) or MII (nibble-wide) / RMII (di-bit-wide) and Receive module will
detect Start of Frame.
Once it verifies a valid sync pattern, a frame will be stored in the MAC Receive FIFO starting from
the destination address field. The state machine also monitors total number of bytes in a frame by
looking at data length field. When the level of the MAC Receive FIFO is more than the threshold
value, the stored frame will be read to the System Receive FIFO at system clock speed. Another
state machine running at the system clock speed will detect destination address, data length, and
CRC for validity of the frame. The destination address is sent to Address Compare Block for
comparison with the stored MAC addresses. If the destination address is found to be a valid address,
then the frame will be written into the System Receive FIFO. If the received address is a multicast
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