參數(shù)資料
型號: HMS30C7202
廠商: HYNIX SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-bit ARM7TDMI RISC static CMOS CPU core
中文描述: 32-BIT, 82.944 MHz, RISC PROCESSOR, PBGA256
封裝: 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-256
文件頁數(shù): 136/161頁
文件大小: 973K
代理商: HMS30C7202
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
136
Register
Address
R/W
Description
Reset value
INTPND
0x10
R/W
0 = The interrupt has not been requested
1 = The interrupt source has asserted a request
0x00000000
Each field and the corresponding bit position are the same as those of SRCPND register.
2.12.1.6.
INTERRUPT OFFSET REGISTER (INTOFS, offset = 0x14)
If INTPND[n] is set to 1 (due to interrupt requests from sources), number “n” is shown in this
register. This is for the ease of an interrupt target address computation, i.e., target address =
INTOFS << 2.
Note that the valid value of this register is 0 – 31 when an interrupt occurs. If it is 32, it means that
there happens no interrupts, i.e., INTPND = 0.
Table 2.102 Interrupt Offset Register
Address :
1930_0014
Register
Address
R/W
Description
Reset value
INTOFS
0x14
R
“n” in 0 – 31 if INTPND[n] is set to 1.
32 if there happens no interrupt.
0x00000020
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