參數(shù)資料
型號: HMS30C7202
廠商: HYNIX SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-bit ARM7TDMI RISC static CMOS CPU core
中文描述: 32-BIT, 82.944 MHz, RISC PROCESSOR, PBGA256
封裝: 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-256
文件頁數(shù): 55/161頁
文件大?。?/td> 973K
代理商: HMS30C7202
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
55
10 = 32 bit wide bus
11 = Reserved
External pull-up/downs on ADDR19 and ADDR18 applies for booting
configuration. Boot program should be appeared on nRCS0. Can be
changed by Configuration 0 afterward.
23:20 RW
0x3
0xf
ASTB TIME
This 4-bit field selects the pulse width of the address strobe signal when
A/D mux bus mode is on.
19:16 RW
0x3
0xf
ADDR TIME
This 4-bit field selects the address phase interval when A/D mux bus
mode is on.
15:12 RW
0x0
0xf
RECOVERY TIME
This 4-bit field selects the recovery time delay, this value guarantee the
interval from the end of one chip select assertion to the start of another
chip select assertion.
11: 8
RW
0x0
0xf
SETUP TIME
This 4-bit field selects the setup time duration, this value guarantees the
interval from chip select assertion to read enable or write enable
assertion.
7: 4
RW
0xf
ACCESS TIME
This 4-bit field selects the access time and this value guarantees the
asserted pulse width of read enable or write enable signal.
3: 0
RW
0xf
HOLD TIME
This 4-bit field selects the hold time duration and this value guarantees
the interval from read enable or write enable de-assertion to chip select
de-assertion.
Note: The first value in the boxes with two defaults values show the default for
ROM Bank0 and the second value for the remaining two Banks, Bank1 and
Bank2.
Note: All units are based on the main clock period.
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