參數(shù)資料
型號： HMS30C7202
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-bit ARM7TDMI RISC static CMOS CPU core
中文描述： 32-BIT, 82.944 MHz, RISC PROCESSOR, PBGA256
封裝： 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-256
文件頁數(shù)： 4/161頁
文件大小： 973K
代理商： HMS30C7202
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
４
Contents
1. Product Overview...................................................................................................................................12
1.1.
Summary of HMS30C7110 features.....................................................................................................13
1.2.
Block Diagram.........................................................................................................................................16
1.3.
Pin Assignments.......................................................................................................................................17
1.4.
Package Pin Diagram (PQ208) ................................................................................................................25
1.5.
Pin Description.........................................................................................................................................26
2.
Functional Description ...........................................................................................................................30
2.1.
System Configuration ..............................................................................................................................32
2.1.1.
Power-up Configuration..................................................................................................................32
2.1.2.
System Memory Map .....................................................................................................................32
2.1.3.
Registers Map.................................................................................................................................35
2.1.4.
ARM7TDMI Core..........................................................................................................................41
2.2.
Cache .......................................................................................................................................................42
2.2.1.
Architecture....................................................................................................................................42
2.2.2.
User Accessible Registers (Base = 0x1950_0000)..........................................................................42
2.3.
Clock/Watchdog Timer ............................................................................................................................46
2.3.1.
Block Diagram................................................................................................................................46
2.3.2.
User Accessible Registers (Base = 0x1830_0000)..........................................................................47
2.4.
Memory Controller (Flash/ROM)............................................................................................................52
2.4.1.
Block Diagram................................................................................................................................52
2.4.2.
User Accessible Registers (Base = 0x1900_0000)..........................................................................53
2.4.3.
Timing Diagram..............................................................................................................................56
2.5.
Memory Controller (SDRAM).................................................................................................................57
2.5.1.
Block Diagram................................................................................................................................57
2.5.2.
User Accessible Registers (Base = 0x1908_0000)..........................................................................58
2.5.3.
Timing Diagram..............................................................................................................................63
2.6.
Ethernet MAC..........................................................................................................................................67
2.6.1.
Block Diagram................................................................................................................................67
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