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參數(shù)資料
| 型號(hào)： | HMS30C7202 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-bit ARM7TDMI RISC static CMOS CPU core |
| 中文描述： | 32-BIT, 82.944 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-256 |
| 文件頁(yè)數(shù)： | 43/161頁(yè) |
| 文件大?。?/td> | 973K |
| 代理商： | HMS30C7202 |
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HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
43
0 – Out HBURST as 3’b011 (Increment 4)
1 – Out HBURST as 3’b001 (Increment)
18
RW
0x0
This bit controls the use of cache.
0 – Cache is used for Data and Instruction (Unified)
1 – Cache is used only for Instruction (I-Cache)
17
RW
0x0
This bit controls the “bufferability” of write accesses to cacheable areas.
0 – accesses to cacheable area are not stored into the write buffer.
1 – accesses to cacheable area are stored into the write buffer.
Buffering write accesses to cacheable area can increase the performance,
but in some cases it may cause problems. So it should be used with care.
We recommend using the default value (non-bufferable) if user is not
sure how to handle the consistency problem.
16
W
0x0
This bit flushes the current contents of the write buffer to the main
memory (1 – flush). This is recommended to be used only when the
cache is off. Normally it is better to read the same address of the
previous write to flush the write buffer.
15:13 RW
0x0
These 3 bits control the burst length of the write buffer’s write operation.
Value 0-7 means 1-8 burst length. As an example, burst length 1 means
that write buffer tries to write the content of the buffer as soon as at least
one access comes into the buffer, and only one write access will be
performed at a time. On the other hand, burst length 8 means that the
write buffer will wait till there comes 8 write accesses into write buffer,
and those accesses will be written to main memory in a single burst
access.
Generally, the larger the burst length, the higher the bus efficiency. But
the latency (from the time CPU writes a data to the actual writing to
main memory) will increase as you use larger burst length.
12
RW
0x0
This bit controls the “bufferability” of write accesses to non-cacheable
areas.
0 – accesses to non-cacheable area are not stored into the write buffer.
1 – accesses to non-cacheable area are stored into the write buffer.
Buffering write accesses to non-cacheable area can increase the
performance, but in some cases it may cause problems. So it should be
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HMS30C7202N | Highly-intergrated MPU |
| HMS81C2012A | CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver |
| HMS81C2012AK | CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver |
| HMS81C2012ALQ | CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver |
| HMS81C2012AQ | INDUCTOR*100UH*0.73AMP*0.672OHM*15%*SURFACE MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMS30C7202N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Highly-intergrated MPU |
| HMS30C7210 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ARM Based 32-Bit Microprocessor |
| HMS3224M3 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
| HMS3224M3-10 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
| HMS3224M3-12 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
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