參數(shù)資料
型號： HMS30C7202
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-bit ARM7TDMI RISC static CMOS CPU core
中文描述： 32-BIT, 82.944 MHz, RISC PROCESSOR, PBGA256
封裝： 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-256
文件頁數(shù)： 128/161頁
文件大小： 973K
代理商： HMS30C7202
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
128
2.12.
INTC
The interrupt controller of HMS30C7110 receives the request from 21 interrupt sources. Among
21, 8 come from outside of chip, i.e., external interrupt sources, and remaining 13 come from
internal sources such as DMA controller, ENET MAC, and etc.
The role of the interrupt controller is to ask for IRQ and/or NMI to the ARM7TDMI after selecting
one among 21 sources based on the arbitration rule. The arbitration is performed by the hardware
priority logic and the result is written to the interrupt pending register to let users to know which
interrupt has been requested.
Interrupt Mode
INTC supports 2 types of interrupt modes, NMI and IRQ. The mode of each interrupt source can be
set by programming interrupt mode register. Among 21 sources, only one, generally very urgent one
such as power failure can be set to operate as NMI.
Interrupt Pending Register
There are two interrupt pending registers. One is source pending register (SRCPND) and the other
is interrupt pending register (INTPND). These pending registers indicate whether or not an interrupt
request is pending. When the interrupt sources request interrupt services the corresponding bits of
SRCPND register are set to 1, and at the next clock cycle one bit of INTPND register corresponding
to the highest priority one is set to 1 after the arbitration process. If some of interrupts are masked
(by programming mask register), the corresponding bits of INTPND register are not set to 1, while
the corresponding bits of SRCPND register are set to 1. When a pending bit of INTPND register is
set, IRQ is generated and goes to CPU. The SRCPND and INTPND registers can be read and
written. The interrupt service routine must clear the pending condition by writing a 1 to the
corresponding bit of SRCPND register first and then clear the pending condition in INTPND
registers by writing 1.
The NMI shares the SRCPND register with IRQ, but it does not go through the arbitration logic and
directly goes to CPU for a fast service. So, in the service routine of NMI, user needs to clear only
the SRCPND register.
Interrupt Mask Register
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