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| 型號(hào)： | HMS30C7202 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-bit ARM7TDMI RISC static CMOS CPU core |
| 中文描述： | 32-BIT, 82.944 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-256 |
| 文件頁(yè)數(shù)： | 44/161頁(yè) |
| 文件大小： | 973K |
| 代理商： | HMS30C7202 |
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HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
44
used with care. For example, write to control registers may require the
“read again” the same address to flush the write buffer.
11:6
RW
0x0
Specify the set to invalid or flush (write back) – 0 to 63
5:4
RW
0x0
Specify the way to invalid or flush (write back) – 0 to 3
3
W
0x0
Line flush (write back)
This bit flushes (write back) a cache line (4 words) corresponding to a
specific way and a set specified in bit [5:4] and [11:6], respectively. It
checks the dirty bit of a given line, write back if necessary, and then
clears the valid bit. This should be activated only when the cache is off.
This bit is automatically cleared to 0 as soon as the write back finishes.
(Actually when cache is off, it finishes immediately even before to
execute the next following instruction.) This bit is used for the
consistency between the cache and the main memory after the cache is
off – i.e., writes the contents of the cache if they are different (new) from
those of main memory (old).
2
W
0x0
Line invalidate
This bit invalidates a cache line (4 words) corresponding to a specific
way and a set specified in bit [5:4] and [11:6], respectively. This clears
the valid bit of a given line without writing the contents of the line to
main memory. This should be activated only when the cache is off. This
bit is automatically cleared to 0 as soon as the invalidation finishes.
(Actually when cache is off, invalidation finishes immediately even
before to execute the next following instruction.)
1
RW
0x0
Parallel/Sequential control (0 – parallel, 1 – sequential)
This bit controls the access sequence of tag RAM and data RAM.
Parallel access of tag RAM and data RAM is for high performance,
while sequential access is for low power operations.
0
RW
0x0
Cache on/off (0 – off, 1 – on)
This bit controls the on and off the cache. After reset, all the valid bits of
cache are cleared to 0. So there are no required procedures to turn on the
cache in the initial state. However, there should be some caution when
turn off the cache since even if the cache is turned off, all the operations
of the cache except the line fill is performed as usual. For example, a
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HMS30C7202N | Highly-intergrated MPU |
| HMS81C2012A | CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver |
| HMS81C2012AK | CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver |
| HMS81C2012ALQ | CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver |
| HMS81C2012AQ | INDUCTOR*100UH*0.73AMP*0.672OHM*15%*SURFACE MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMS30C7202N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Highly-intergrated MPU |
| HMS30C7210 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ARM Based 32-Bit Microprocessor |
| HMS3224M3 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
| HMS3224M3-10 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
| HMS3224M3-12 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
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