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參數(shù)資料
| 型號： | HDMP-1024 |
| 英文描述： | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價格千兆位速率接收芯片) |
| 中文描述： | 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價格千兆位速率接收芯片） |
| 文件頁數(shù)： | 9/40頁 |
| 文件大小： | 363K |
| 代理商： | HDMP-1024 |
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9
Clock Select
The Clock Select accepts the high
speed digital signal from the VCO
and outputs an internal high
speed serial clock. The VCO
frequency is divided, based on the
DIV1/DIV0 inputs, to the input
signal’s frequency range. The
Clock Select output is an internal
serial clock. It is phase and
frequency locked to the incoming
signal. This internal serial clock is
used by the Input Sampler to
sample the data. It is also used by
the Clock Generator to generate
the recovered frame rate clock.
By setting TCLKSEL high, the
user may input an external serial
clock at TCLK. The Clock Select
accepts this signal and directly
outputs it as the internal serial
clock. TCLKSEL is not
characterized.
Clock Generator
The Clock Generator accepts the
serial clock generated from the
Clock Select and generates the
frame rate clock, based on the
setting of M20SEL. If M20SEL is
asserted, the incoming encoded
data frame is expected to be 24
bits wide (20 data bits and 4
control bits). In this case the
master transition in the control
section of encoded data stream is
expected every 24 bits, and used
to ensure proper frame syn-
chronization of the output frame
clock, STRBOUT.
Input Sampler
The serial input signal is con-
verted into a serial bit stream,
using the extracted internal serial
clock from the Clock Select. This
output is sent to the frame
demux.
Frame Demux
The Frame Demux demultiplexes
the serial bit stream from the
Input Sampler into a 20 or 24 bit
wide parallel data word, based on
the setting of M20SEL. The most
significant 4 bits are sent to the
C-Field Decoder, while the
remaining 16 or 20 bits are sent
to the D-Field Decoder.
C-Field Decoder
The C-Field Decoder accepts the
control information from the
Frame Demux and determines
what kind of frame is being
received and whether or not it has
to be inverted. The control bits
are sent to the State Machine for
error checking. The decoded
information is sent to the D-Field
Decoder. CAV* is set low if the
incoming frame is control data.
When CAV* is low, the state of
DAV* is “don’t care”. DAV* is set
low if the information is data. If
neither DAV* nor CAV* is set low,
then the incoming frame is
expected to be a fill frame. If
FLAGSEL is asserted, the FLAG
bit is restored to its original form.
If FLAGSEL is not asserted, FLAG
is used to differentiate between
the even and odd frames in
Double Frame Mode. For more
information about this, refer to
Double Frame Mode
.
D-Field Decoder
The D-Field Decoder accepts the
data field of the incoming data
frame from the Frame Demux.
Based on information from the C-
Field Decoder, which determines
what type of data is being
received, the D-Field Decoder
restores the parallel data back to
its original form.
State Machine
The State Machine is used in full
duplex mode to perform the
functions of link startup, link
maintenance, and error checking.
By setting the SMRST0* and
SMRST1* low, the user can reset
the state machine and initiate link
startup. SMRST1* is usually
connected to the transmitter’s
LOCKED output. STAT1 and
STAT0 denote the current state of
link during startup. ACTIVE is an
input normally driven by the
STAT1 output. This ACTIVE input
is retimed by STRBOUT and
presented to the user as
LINKRDY*. LINKRDY* is an
active low output that indicates
when the link is ready to transmit
data. Refer to
The State Machine
Handshake Protocol
section on
page 30 for more details.
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| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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