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參數(shù)資料
| 型號(hào)： | HDMP-1024 |
| 英文描述： | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片) |
| 中文描述： | 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價(jià)格千兆位速率接收芯片） |
| 文件頁(yè)數(shù)： | 15/40頁(yè) |
| 文件大?。?/td> | 363K |
| 代理商： | HDMP-1024 |
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15
Tx I/O Definition
Name
CAP0B
CAP1B
Pin
1
4
Type
C
Signal
Loop Filter Capacitor:
A loop filter capacitor of 0.1
μ
F
must be connected across the CAP0B and CAP1B inputs to
increase the loop time constant.
Control Word Available Input:
This active-low input tells the chip
that the user is requesting a control word be transmitted. This pin
should only be asserted after the user has determined the RFD line is
active for a given frame cycle. When this pin is asserted, the
information on the Data inputs is sent as a control frame. If CAV* and
DAV* are asserted simultaneously, CAV* takes precedence.
Data Inputs:
20 Bit data is encoded and transmitted when M20SEL
is active; otherwise the 16 least significant bits are encoded and
transmitted. The encoded bits are transmitted LSB first (e.g.: D0 is
sent first, through to either D15 or D19, followed by the 4 coding bits
C0-C3).
CAV*
69
I-TTL
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
DAV*
59
58
57
56
55
54
53
51
50
49
48
47
46
45
40
39
38
37
36
35
70
I-TTL
I-TTL
Data Available Input:
This active-low input tells the chip that the
user has valid data to be transmitted. This pin should be asserted only
after the user has determined that the RFD line is active for a given
frame cycle. When this pin is asserted, the information on the Data
and Flag inputs is encoded and sent as a data frame.
VCO Divider Select:
These two pins program the VCO divider chain
to operate at full speed, half speed, quarter speed, or one-eighth speed.
Normal Serial Data Output:
Output used when LOOPEN is not
active. This output is a special
buffer line logic
driver, which is a 50
back-terminated ECL compatible output.
Enable Data:
This signal comes from the Rx chip state machine and
is used to control the RFD output of the Tx chip. The state machine
only allows data to be enabled when both sides of the link have
established stable lock.
DIV0
DIV1
DOUT
DOUT*
19
20
17
18
I-TTL
O-BLL
ED
67
I-TTL
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相關(guān)代理商/技術(shù)參數(shù) |
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| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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