參數(shù)資料
型號(hào)： HDMP-1024
英文描述： Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片)
中文描述： 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價(jià)格千兆位速率接收芯片）
文件頁數(shù)： 20/40頁
文件大小： 363K
代理商： HDMP-1024
20
Rx I/O Definition (cont’d.)
Name
Pin
ERROR
40
Type
O-TTL
Signal
Received Data Error:
Asserted when a frame is received that does
not correspond to either a
valid
Data, Control, or Fill frame encoding.
When FLAGSEL is not active, the Rx chip also tests for strict
alternation of flag bits during data frames. A flag bit alternation
error will also cause an ERROR indication.
Frequency Detector Disable Input:
When active, this input
disables the Rx PLL Frequency detector and enables a phase detector.
The Frequency detector is used during the start-up sequence to
acquire wide-band lock on Fill Frames, but must be disabled prior to
sending data patterns. This input is normally controlled by the Rx
state machine.
Fill Frame Status:
During a given STRBOUT clock cycle, if neither
DAV*, CAV*, or ERROR are active, then the currently received frame
is a Fill frame. The type of fill frame received is indicated by the FF
pin. If FF is low, then FF0 has been received. If FF is high, then
either FF1a or FF1b has been received.
Flag Bit:
If both Tx and Rx have FLAGSEL asserted, this output
indicates the value of the transmitted flag bit, and this received bit
can be treated just like an extra data bit. If both Tx and Rx have
FLAGSEL set to low, FLAG is used to differentiate the even frame
from the odd frame in the line code.
Flag Bit Mode Select:
When this input is high, the extra FLAG bit
output is effectively an extra transparent data bit. Otherwise, the
FLAG bit is checked for alternation during data frames. Any break in
strict alternation results in an ERROR indication to the user.
TTL Ground:
Normally 0 Volts. Tie to ground.
FDIS
20
I-TTL
FF
39
O-TTL
FLAG
45
O-TTL
FLAGSEL
34
I-TTL
GND
TTL
31
41
61
74
11
21
22
42
43
62
79
80
18
17
S
GND
S
Ground:
Normally 0 Volts. Tie to ground.
LIN
LIN*
I-H50
Loop Back Serial Data Input:
Use this input when LOOPEN is
active. Unlike the DIN, DIN* inputs, this input does not have a cable
equalizer. In normal usage, this input will be connected to the Tx
chip LOUT, LOUT* outputs. This allows the user to check the
near-end functionality of the Tx and Rx pair independent of the
transmission medium.
Loop Back Control:
When asserted, this signal causes the loop back
data inputs LIN, LIN* to be used instead of the normal data inputs
DIN, DIN*.
Link Ready Indicator:
This active-low output is a retimed version
of the ACTIVE input. ACTIVE is normally driven by the Rx state
machine output. LINKRDY* then indicates that the startup sequence
is complete and that the data and control indications are valid.
LOOPEN
16
I-TTL
LINKRDY*
36
O-TTL
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