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參數(shù)資料
| 型號(hào)： | HDMP-1526 |
| 英文描述： | Transistor Diode Kit;Contents Of Kit:Transistor/Diode Kit |
| 中文描述： | 光纖通道收發(fā)器芯片 |
| 文件頁(yè)數(shù)： | 1/14頁(yè) |
| 文件大?。?/td> | 229K |
| 代理商： | HDMP-1526 |
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682
Fibre Channel Transceiver Chip
Technical Data
HDMP-1526 Transceiver
Features
ANSI X3.230-1994 Fibre
Channel Compatible (FC-0)
Supports Full Speed
(1062.5 MBd) Fibre Channel
Conforms to “Fibre Channel
10-Bit Interface”
Specification
Transmitter and Receiver
Functions Incorporated onto
a Single IC
10-Bit Wide Parallel TTL
Compatible I/Os
Single +5.0 V Power Supply
Applications
1062.5 MBd Fibre Channel
Interface
Mass Storage System I/O
Channel
Work Station/Server I/O
Channel
High Speed Proprietary
Interface
Description
The HDMP-1526 transceiver is a
single silicon bipolar integrated
circuit packaged in an EDQuad
package. It provides a low-cost,
low-power physical layer solution
for 1062.5 MBd Fibre Channel or
proprietary link interfaces. It
provides complete FC-0 func-
tionality for copper transmission,
incorporating both the Fibre
Channel FC-0 transmit and
receive functions into a single
device.
This chip is used to build a high-
speed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with both the ANSI
X3.230-1994 document and the
“Fibre Channel 10-bit Interface”
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a high-
speed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or
equivalent. This parallel data is
latched into the input register of
the transmitter section on the
rising edge of the 106.25 MHz
reference clock (used as the
transmit byte clock).
The transmitter section’s PLL
locks to this user supplied 106.25
MHz byte clock. This clock is
multiplied by 10, to generate the
1062.5 MHz serial signal clock
used to generate the high-speed
output. The high-speed outputs
are capable of interfacing directly
to copper cables for electrical
transmission or to a separate
fiber-optic module for optical
transmission.
The receiver section accepts a
serial electrical data stream at
1062.5 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high-speed serial
clock and data. The serial data is
converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 53.125
MHz receiver byte clocks that are
180 degrees out of phase with
each other. The parallel data is
aligned with the rising edge of
alternating clocks.
The transceiver provides for on-
chip local loop-back functionality,
controlled through an external
input pin. Additionally, the byte
synchronization feature may be
disabled. This may be useful in
proprietary applications that use
alternative methods to align the
parallel data.
5964-6897E (5/96)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-1536 | Fibre Channel Transceiver Chip |
| HDMP-1546 | Fibre Channel Transceiver Chip |
| HDMP-1546A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| HDMP-1536A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| HDMP-1636 | Software |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1536 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
| HDMP-1536A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fiber-Optic Transceiver |
| HDMP-1546 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
| HDMP-1546A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-TRANSCEIVER |
| HDMP-1636 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip |
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