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參數(shù)資料
| 型號(hào)： | HDMP-1024 |
| 英文描述： | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片) |
| 中文描述： | 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價(jià)格千兆位速率接收芯片） |
| 文件頁(yè)數(shù)： | 33/40頁(yè) |
| 文件大?。?/td> | 363K |
| 代理商： | HDMP-1024 |
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33
data (RFD). Other configurations
for duplex mode are also possible
with external user-defined state
machines. Simplex operation
using G-LINK is also possible. The
following sections discuss three
different types of simplex
configurations.
Simplex Method I. Simplex
with Low-Speed Return Path
Low-speed lines are used in the
simplex method of Figure 17a.
The remote Rx controls the states
of both the Rx and the local Tx
using these low speed lines. This
is ideal for cases where these non-
critical lines are available. Again,
a power on reset is available to
the user. This connection between
the Tx and Rx is identical to one
side of the duplex configuration.
When the Tx is locked, the Rx is
enabled via the LOCKED line. The
Rx’s STAT0 and STAT1 outputs
are low, causing the local Tx to
send FF0. When the Rx is frame
locked, STAT1 is raised, which
disables its frequency detector,
sets itself to active mode, and tells
Tx to send FF1. Upon receiving
FF1 from the Tx, the Rx’s STAT0
line is raised, which enables the
Tx (ED) for data transmission. If
desired, the Rx reset pin
(SMRST1*) can be tied high, and
the LOCKED line can be
eliminated.
Simplex Method II. Simplex
with Periodic Sync Pulse.
Another configuration of simplex
operation is shown in Figure 17b.
For frame lock, the Rx normally
Figure 17. Simplex Configurations.
Tx DATA
INTERFACE
DOUT
R
L
E
F
OPTIONS
Rx DATA
INTERFACE
DIN
A
F
S
S
S
S
LIN
Rx
Tx
POWER-ON
RESET
LOUT
POWER-ON
RESET
OPTIONS
Tx DATA
INTERFACE
DOUT
R
L
E
F
OPTIONS
Rx DATA
INTERFACE
DIN
A
F
S
S
S
S
LIN
Rx
Tx
POWER-ON RESET
PERIODIC
SYNC PULSES
LOUT
POWER-ON
RESET
OPTIONS
Tx DATA
INTERFACE
DOUT
R
L
E
F
OPTIONS
Rx DATA
INTERFACE
LIN
A
F
S
S
S
S
DIN
Rx
Tx
POWER-ON
RESET
LOUT
POWER-ON
RESET
OPTIONS
LOW SPEED LINES
A) SIMPLEX METHOD 1 WITH LOW-SPEED RETURN PATH
B) SIMPLEX METHOD 2 WITH PERIODIC SYNC PULSE
L
OSC
C) SIMPLEX METHOD 3 WITH EXTERNAL REFERENCE OSCILLATOR
FREQ = FRAME RATE
V
CC
V
CC
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| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
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| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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