參數(shù)資料
型號： HDMP-1024
英文描述： Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片)
中文描述： 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價(jià)格千兆位速率接收芯片）
文件頁數(shù)： 2/40頁
文件大小： 363K
代理商： HDMP-1024
2
Table of Contents
Topic
........................................................................................................................................................Page
Typical Applications....................................................................................................................................... 3
Setting the Operating Rate ............................................................................................................................. 4
Transmitter Block Diagram............................................................................................................................ 6
Receiver Block Diagram................................................................................................................................. 8
Transmitter Timing Characteristics.............................................................................................................. 10
Receiver Timing Characteristics................................................................................................................... 11
DC Electrical Specifications......................................................................................................................... 12
AC Electrical Specifications ......................................................................................................................... 12
Typical Lock-Up Times ................................................................................................................................ 12
Latency ........................................................................................................................................................ 12
Absolute Maximum Ratings.......................................................................................................................... 13
Thermal Characteristics ............................................................................................................................... 13
I/O Type Definitions ..................................................................................................................................... 13
Pin-Out Diagrams ........................................................................................................................................ 13
Transmitter Pin Definitions .......................................................................................................................... 15
Receiver Pin Definitions............................................................................................................................... 19
Mechanical Dimensions and Package Information........................................................................................ 22
Recommended Handling Precautions........................................................................................................... 22
Appendix I: Additional Internal Architecture Information
................................................................. 23
Line Code Description ................................................................................................................................. 23
Data Frame Codes ....................................................................................................................................... 23
Control Frame Codes ................................................................................................................................... 24
Fill Frame Codes.......................................................................................................................................... 25
Tx Operation Principles ............................................................................................................................... 26
Tx Encoding ................................................................................................................................................ 26
Tx Phase Locked Loop................................................................................................................................. 27
Rx Operation Principles ............................................................................................................................... 28
Rx Encoding ................................................................................................................................................ 28
HDMP-1024 (Rx) Phase Locked Loop ......................................................................................................... 29
HDMP-1024 (Rx) Decoding ......................................................................................................................... 29
HDMP-1024 (Rx) Link Control State Machine Operation Principle .............................................................. 30
The State Machine Handshake Protocol ....................................................................................................... 30
Appendix II: Link Configuration Examples
.......................................................................................... 32
Duplex/Simplex Configurations.................................................................................................................... 32
Full Duplex .................................................................................................................................................. 32
Simplex Method I: Simplex with Low Speed Return Path ............................................................................ 33
Simplex Method II: Simplex with Periodic Sync Pulse ................................................................................. 33
Simplex Method III: Simplex with External Reference Oscillator................................................................. 34
Data Interface for Single/Double Frame Mode.............................................................................................. 34
Single Frame Mode (MDFSEL=0)................................................................................................................ 35
Double Frame Mode (MDFSEL=1).............................................................................................................. 35
Supply Bypassing and Integrator Capacitor ................................................................................................. 36
Integrating Capacitor ................................................................................................................................... 37
Power Supply Bypassing and Grounding...................................................................................................... 37
Electrical Connections ................................................................................................................................. 38
I-TTL and O-TTL .......................................................................................................................................... 38
High Speed Interface: I-H50 & O-BLL ......................................................................................................... 38
Mode Options .............................................................................................................................................. 39
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HDMP-1032 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1032A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1034 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
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