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參數(shù)資料
| 型號： | HDMP-1024 |
| 英文描述： | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價格千兆位速率接收芯片) |
| 中文描述： | 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價格千兆位速率接收芯片） |
| 文件頁數(shù)： | 24/40頁 |
| 文件大?。?/td> | 363K |
| 代理商： | HDMP-1024 |
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24
HDMP-1022 (Tx), HDMP-1024 (Rx)
Operating Modes
M20SEL
FLAGSEL
0
0
0
1
1
0
1
1
Description
16 bit data plus error checking
16 bit data plus FLAG
20 bit data plus error checking
20 bit data plus FLAG
Data Frame Structure
M20SEL Not Asserted (16 bit data mode)
Data Status
True
Inverted
True
Inverted
Flag bit
0
0
1
1
D-Field
D
0
-
D
15
D
0
-
D
15
D
0
-
D
15
D
0
-
D
15
C-Field
1101
0010
1011
0100
Data Frame Structure
M20SEL Asserted (20 bit data mode)
Data Status
True
Inverted
True
Inverted
Flag bit
0
0
1
1
D-Field
D
0
-
D
19
D
0
-
D
19
D
0
-
D
19
D
0
-
D
19
C-Field
1101
0010
1011
0100
Control Frame Codes
There are 2
18
control words
provided in 20 bit mode. If the
user desires to send a control
word, his lower 9 bits (
D0-D8
)
are sent as bits D0-D8 of the D-
Field. The next 9 bits (
D9-D17
)
are sent as bits D11-D19 of the
D-Field. The control frame is
either inverted or not inverted as
needed to maintain balance, with
the coding bits 0011 used to
indicate true control, and the bits
1100 used to indicate
complement control. The bits D9
and D10 are always forced to 0 1
for true control frames and 1 0
for complement control frames.
These middle bits are used to
distinguish control frames from
fill frames, which always have the
middle bits set to either 00, 11, or
10. Similarly, there are 2
14
control words provided in 16 bit
mode.
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| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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