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參數(shù)資料
| 型號： | HDMP-1034 |
| 英文描述： | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| 中文描述： | 1.4 GBd接收芯片組與CIMT編碼器/解碼器和可變數(shù)據(jù)速率（帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd接收器） |
| 文件頁數(shù)： | 1/32頁 |
| 文件大?。?/td> | 346K |
| 代理商： | HDMP-1034 |
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Agilent HDMP-1032/1034
Transmitter/Receiver
Chip Set
Data Sheet
Features
3.3 V supply, low power
dissipation
590 mW Tx, 660 mW Rx
On-chip encode/decode using
Conditional Inversion Master
Transition (CIMT) protocol
1:N broadcast ready
configurable receiver inputs allow
multi-point data broadcast using a
single transmitter
Parallel Automatic
Synchronization System (PASS)
allows receiver to read recovered
words with local reference clock
Robust simplex mode
Wide range serial rate
260-1400 MBaud (user selectable)
5 V tolerant TTL interface
16 or 17 Bits wide
Low cost 64 pin plastic package
14x14 mm
2
PQFP
Applications
Cellular base station
ATM switch
Backplane/bus extender
Video, image acquisition
Point to point data link
Implement SCI-FI standard
Description
The HDMP-1032 transmitter and
HDMP-1034 receiver are used
together to build a high-speed
data link for point-to-point
communication. These silicon
bipolar transmitter and receiver
chips are housed in standard
plastic 64 pin PQFP packages.
From the user’s viewpoint, these
products can be thought of as a
“virtual ribbon cable” interface for
the transmission of data and con-
trol words. A parallel word loaded
into the Tx (transmitter) chip is
delivered to the Rx (receiver)
chip over a serial channel and is
then reconstructed into its origi-
nal parallel form. The channel
can be either a coaxial copper
cable or optical link
The chip set hides from the
user the complexity of encoding,
multiplexing, clock extraction,
demultiplexing and decoding. The
CIMT encoding scheme used en-
sures the DC balance of the serial
line. When data or control words
are not being sent the transmitter
sends idle words.
The serial data rate of the Tx/Rx
link is selectable in three ranges
and extends from 208 to 1120
Mbit/s. This translates into an
encoded serial rate of 260 to
1400 MBaud. The parallel data
interface is 16 bit TTL. A flag bit
is also present and can be used as
an extra 17th bit under the user’s
control. This bit can be used as
an even or odd word indicator
for dual-word transmission. The
encoding of the flag bit can be
scrambled to reduce the probabil-
ity of erroneous word alignment.
A user control space is also
provided. If TXCNTL is asserted
on the Tx chip, the least signifi-
cant 14 bits of the data will be
sent and the RXCNTL line on the
Rx chip will indicate the data is
a Control Word.
At the Rx, the PASS feature
allows the recovered words to
be clocked out with the local
1.4 GBd Transmitter/Receiver Chip Set with
CIMT Encoder/Decoder and Variable Data Rate.
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| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
| HDMP-1514 | Fibre Channel Receiver Chipset(光纖通道接收芯片) |
| HDMP-1526 | Transistor Diode Kit;Contents Of Kit:Transistor/Diode Kit |
| HDMP-1536 | Fibre Channel Transceiver Chip |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
| HDMP-1514 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
| HDMP1526 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| HDMP-1526 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
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