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參數(shù)資料
| 型號： | HDMP-1024 |
| 英文描述： | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價格千兆位速率接收芯片) |
| 中文描述： | 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價格千兆位速率接收芯片） |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 363K |
| 代理商： | HDMP-1024 |
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17
Tx I/O Definition (cont’d.)
Name
LOCKED
Pin
75
Type
O-TTL
Signal
Loop In-lock Indication:
This signal indicates the lock status of the
Tx PLL. A high value indicates lock. This signal is normally connected
to the SMRST1* reset input of the Rx state machine to force the into the
start-up state until the Tx PLL has locked. This signal may
give multiple false-lock indications during the acquisition process, so it
should be debounced if it is used for any other purpose than to drive
the Rx chip.
Loop Back Control:
Input which controls whether the DOUT,
DOUT*, or the LOUT, LOUT* outputs are currently enabled. If active,
LOUT, LOUT* are enabled. The unused output is powered down to
reduce dissipation.
LOOPEN
16
I-TTL
LOUT
LOUT*
14
15
O-BLL
Loop Back Serial Data Output:
Output used when LOOPEN is
active. Typically this output will be used to drive the LIN, LIN* inputs
of the Rx chip.
16 or 20 Bit Word Select:
When this signal is high, the link operates
in 20 Bit data transmission mode. Otherwise, the link operates in
16 Bit mode.
Select Double Frame Mode:
When this signal is high, the PLL
expects a 1/2 speed frame rate clock at STRBIN. The chip then
internally multiplies this clock and produces a full-rate parallel clock at
STRBOUT. Note that the phase relationship of STRBIN to STRBOUT
and the sampling point change with asserting MDFSEL, as shown in
the Tx timing diagram. This feature is provided so that either a 40 bit
or 32 bit word can be easily transmitted as two 20, or two 16 bit
words. When MDFSEL is low, the PLL expects a full-rate parallel
clock at STRBIN.
No connection. These pins are not bonded internally.
M20SEL
73
I-TTL
MDFSEL
74
I-TTL
NC
2
3
65
RFD
O-TTL
Ready for Data:
Output to tell the user the Link is ready to
transmit data. This pin is a retimed version of the ED input, which is
driven by the Rx chip state machine controller.
Chip Reset:
This active-low pin initializes the internal chip registers.
It should be asserted during power up for a minimum of 5 parallel-
rate clock cycles to ensure a complete reset.
RST*
34
I-TTL
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| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
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