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參數(shù)資料
| 型號(hào)： | HDMP-1024 |
| 英文描述： | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片) |
| 中文描述： | 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價(jià)格千兆位速率接收芯片） |
| 文件頁數(shù)： | 36/40頁 |
| 文件大?。?/td> | 363K |
| 代理商： | HDMP-1024 |
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36
On the Tx side, the expected
frequency is 1/2 of the combined
frame period. This combined
frame, D0-D19, is formed by
interlacing the two frames C0-
C19 and C20-C39 with an
external 2:1 multiplexer. The Tx
locks onto STRBIN, which has the
same frequency as the bit rate of
C0-C39, and with an internal
frequency doubler, generates the
sampling clock to latch in
D0-D19, DAV*, CAV*, and FLAG.
STRBIN is also used to toggle the
2:1 multiplexer, and is fed into
the flag input to signify the two
frames. The setup and hold times
are referenced to 1/2 frame
period plus 4 ns of D0-D19, or 90
degrees, from the edges of
STRBIN. The multiplexer delay,
t
mux
, should be considered for
timing margins. The STRBOUT is
derived from the internal
sampling clock, and thus has a
frequency double that of STRBIN.
The falling edge of STRBOUT
appears after the rising and
falling edges of STRBIN after a
delay of T
strb
. Other interlacing
techniques can also be achieved
with edge-triggered latches for
improved timing margins.
In the Rx side, the frame D0-D19
are demultiplexed back to the
original C0-C19, and C20-C39
frames with the use of external
edge-triggered flip-flops. The
toggle clock of the flip-flops,
RCLK, is derived by the state of
the FLAG bit. RCLK toggles with
the rising edge of STRBOUT with
a delay of t
da
. The two frames
appear with the rising and falling
edges of RCLK with a delay of t
db
.
All of the synchronous outputs
and state machine outputs appear
after the falling edge of STRBOUT
with delays of t
d1
and t
d2
,
respectively.
The lower frame of C0-C19 can
be delayed further with additional
latches so that both C0-C19 and
C20-C39 frames are synchronous.
Supply Bypassing and
Integrator Capacitor
Figure 20 shows the location of
the PLL integrator capacitors,
power supply capacitors and
required grounding for the Tx and
Rx chips.
Figure 19. Transmitter and Receiver Data Interface and Timing for Double Frame Mode (MDFSEL=1).
Tx
CONFIGURATIONS
CAV*, DAV*
C00 - C19
PLL
STRBOUT
STRBIN
Rx
CONFIGURATIONS
CAV*, DAV*, FF
LINKRDY*, ERROR
C00 - C19
STRBOUT
STAT0; STAT1
t
s
t
h
t
strb
CAV*, DAV*
STRBOUT
STRBIN
FLAG
CAV*, DAV*
FF, LINKRDY*
ERROR
D00 - D19
STRBOUT
t
d1
t
s
= SETUP TIME
t
h
= HOLD TIME
t
strb
= STRBIN TO STRBOUT DELAY
t
mux
= 2:1 MULTIPLEXER DELAY
t
d1
= STRBOUT TO SYNCHRONOUS OUTPUTS DELAY
t
d2
= STRBOUT TO STATE MACHINE OUTPUTS DELAY
t
da
= STRBOUT TO RCLK DELAY
t
db
= RCLK TO C00-C39 OUTPUT DELAY
2:1
1
0
D00 - D19
C20 - C39
C20 - C39
D00 - D19
FLAG
FLAG
1/2 FRAME
PERIOD
1/2 FRAME
PERIOD
t
s
t
h
t
s
t
h
D00 - D19
t
s
t
h
C00 - C19
C20 - C39
C00 - C19
C20 - C39
t
mux
t
d2
STAT0
STAT1
FLAG
RCLK
C00 - C19
C20 - C39
C00 - C19
C20 - C39
t
da
t
da
t
db
t
db
RCLK
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