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參數(shù)資料
| 型號(hào)： | HDMP-1024 |
| 英文描述： | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片) |
| 中文描述： | 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價(jià)格千兆位速率接收芯片） |
| 文件頁數(shù)： | 37/40頁 |
| 文件大小： | 363K |
| 代理商： | HDMP-1024 |
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37
Integrating Capacitor
The integrating capacitors (C2)
are required by both the Tx and
Rx to function properly. These
caps are used by the PLL for
frequency and phase lock and
directly set the stability and
lockup times. The designed value
of C2 is 0.1
μ
F, with a tolerance
of
±
10%. The internal charging
currents are scaled with the DIV0
and DIV1 settings such that the
same capacitor value works with
all four frequency bands. Larger
values of C2 improve jitter
performance, but extend the
lockup times.
Power Supply Bypassing and
Grounding
The G-Link chip set has been
tested to work well with a single
power plane, assuming that it is a
fairly clean power plane. Thus, all
of the separate power supplies
(V
CC
, and V
CC
_TTL) can be
connected onto this plane. The
bypassing of V
CC
to ground
should be accomplished with a
capacitor (C1) of 0.1
μ
F.
In some instances, if the VCO of
either the Tx or the Rx are at the
extreme high end, the frequency
of STRBOUT exceeds the maxi-
mum frequency allowed by the
hosts. In this case, it is recom-
mended that a diode clamp, D1,
be used across the integrating cap
C2, such that the upper frequency
Figure 20a. HDMP-1022 (Tx) Power Supply Bypass.
Figure 20b. HDMP-1022 (Rx) Power Supply Bypass.
HDMP-1024
Rx
C2
D1
C1
CAP0B
V
CC
V
CC_HS
V
CC
C1
V
CC
V
CC
C1
V
CC
V
CC
V
C
C1
V
CC
43
V
CCTTL
V
CCTTL
V
CC
V
CC
V
C
C1
V
CC
V
C
C1
V
C
CAP1B
V
C
C1
11
HDMP-1022
Tx
C2
D1
C1
CAP0B
1
CAP1B
V
CC
V
CC
C1
V
CC
V
CC
V
CC
C1
V
CC
V
CC
V
C
V
C
C1
C1
V
CC
V
CC
V
CC
V
CC
V
CC
V
C
V
C
V
C
C1
V
CC
9
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