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參數(shù)資料
| 型號(hào)： | HDMP-1024 |
| 英文描述： | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片) |
| 中文描述： | 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價(jià)格千兆位速率接收芯片） |
| 文件頁數(shù)： | 12/40頁 |
| 文件大?。?/td> | 363K |
| 代理商： | HDMP-1024 |
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12
HDMP-1022 (Tx), HDMP-1024 (Rx)
DC Electrical Specifications
Tc = 0
°
C to +85
°
C, V
CC
= 4.5 V to 5.5 V
Symbol
V
IH,TTL
TTL Input High Voltage Level, Guaranteed high signal for
all inputs
V
IL,TTL
TTL Input Low Voltage Level, Guaranteed low signal for all
inputs
V
OH,TTL
TTL Output High Voltage Level, I
OH
= -400
μ
A
V
OL,TTL
TTL Output Low Voltage Level, I
OL
= 1 mA
I
IH,TTL
Input High Current V
IN
= V
CC
I
IL,TTL
Input Low Current V
IN
= 0 Volts
V
IP,H50
H50 Input Peak-To-Peak Voltage
V
OP,BLL
BLL Output Peak-To-Peak Voltage, Terminated
with 50
, ac coupled
I
CC,Tx
Transmitter V
CC
Supply Current, with HCLKON off.
Typical at 5 V, 25oC, maximum at 5 V, 85oC.
Pattern: 10 pins toggling, 5 pins high, 5 pins low
I
CC,Rx
Receiver V
CC
Supply Current, Typical at 5 V, 25oC,
maximum at 5 V, 85oC. 10pF loading.
Pattern: 10 pins toggling, 5 pins high, 5 pins low
Parameter
Units
V
Min.
2.0
Typ.
Max.
V
CC
V
0
0.8
V
V
2.4
0
V
CC
0.6
4 0
600
μ
A
μ
A
m V
mV
0.004
295
200
500
mA
385
470
mA
500
600
AC Electrical Specifications
Tc = 25
°
C, V
CC
= 4.5 V to 5.5 V
Symbol
t
r,TTLin
t
f,TTLin
t
r,TTLout
t
f,TTLout
t
r
,
BLL
t
f
,
BLL
VSWR
i,H50
VSWR
o,BLL
Parameter
Units
nsec
nsec
nsec
nsec
psec
psec
Min.
Typ.
2
2
1.1
1.5
240
240
2:1
2:1
Max.
Input TTL Rise Time, 0.8 to 2.0 Volts
Input TTL Fall Time, 2.0 to 0.8 Volts
Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF load
Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF load
BLL Rise Time, Terminated with 50
, ac coupled
[1]
BLL Fall Time, Terminated with 50
, ac coupled
[1]
H50 Input VSWR
BLL Output VSWR
2.4
2.4
Note:
1. Rise and fall times are measured from 20% to 80% of the voltage range.
Typical Lock-Up Time
Tc = 25
°
C, V
CC
= 4.5 V to 5.5 V
DIV1
DIV0
HDMP-1022, msec
0
0
0
1
1
0
1
1
Note:
1. Measured in Local Loop-Back mode with the state machine engaged and 0 cable length.
Latency
Tc = 25
°
C, V
CC
= 4.5 V to 5.5 V
Latency
(Clock
Cycles)
Tx
1
Delay measured from the rising edge of STRBIN to the first bit D0 in the serial
stream
Rx
2
Delay measured from the input of the data frame to the falling edge of STRBOUT
when the data frame is updated
Link
3
Delay measured from the rising edge of the Tx STRBIN when the data frame is read
to the falling edge of the Rx STRBOUT when the data frame is updated
HDMP-1024, msec
2.2
3.2
4.7
11.0
LINK
[1]
, msec
2.5
3.5
5.0
12.0
2.0
3.0
4.5
8.0
Latency Definition
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| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
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| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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