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參數(shù)資料
| 型號： | HDMP-1024 |
| 英文描述： | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價格千兆位速率接收芯片) |
| 中文描述： | 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價格千兆位速率接收芯片） |
| 文件頁數(shù)： | 38/40頁 |
| 文件大?。?/td> | 363K |
| 代理商： | HDMP-1024 |
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38
that the unused differential inputs
be terminated with 50
. The
O-BLL output cell is designed to
deliver PECL levels directly into
an AC-coupled 50
load. The
output impedance is matched to
50
with a VSWR of less than
2:1 to above 2 GHz. This output is
ideal for driving the I-H50 input
through a 50
cable and a 0.1
uF coupling capacitor. The O-BLL
driver can also be connected
directly into a high speed 50
oscilloscope. For optimum
performance, both outputs should
see the same impedance. It is
necessary that all used O-BLL
outputs be terminated into 50
.
Figure 23 shows various methods
of interfacing O-BLL to I-H50 and
standard PECL logic.
is limited. The typical swing of C2
is
±
0.8 volts, and thus, the
clamping diode should have a
turn-on voltage below 0.8 V, such
as with germanium or Schottky
diodes. This will vary with each
application. This diode will also
aid the Tx and Rx in the initial
frequency lock-in process.
Electrical Connections
The electrical I/Os for both the Tx
and Rx are shown in Figures 20-
21. The data sheet uses the
prefix, I and O, on the logic type
in order to identify input and
output lines respectively.
Additional information on pin
names and their functions can be
found in the data sheet under
Tx / Rx I/O Definitions
.
I-TTL and O-TTL
These I/O pins are TTL-
compatible. A simplified
schematic diagram of I/O cell is
shown in Figures 21.
High Speed Interface: I-H50 &
O-BLL
The simplified schematic
diagrams of I-H50 and O-BLL is
are shown in Figure 22. The
I-H50 input cell has internal 50
resistors built into the differential
input lines. The termination is
connected via V
CC
_HS which
isolates the high speed supply
currents from the internal
supplies. The DC level for the
inputs is at V
CC
. Since all of the
high speed inputs into G-Link do
not have a DC component, it is
recommended that I-H50 inputs
be AC coupled with a 0.1
μ
F
capacitor. It is also recommended
Figure 21. I-TTL and O-TTL Simplified Circuit Schematic.
800
72
10 k
V
CC
_TTL
O_TTL
I_TTL
10 k
V
CC
_TTL
GND_TTL
6 k
36
GND_TTL
V
BB
1.4 V
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