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參數(shù)資料
| 型號： | HDMP-1024 |
| 英文描述： | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價格千兆位速率接收芯片) |
| 中文描述： | 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價格千兆位速率接收芯片） |
| 文件頁數(shù)： | 7/40頁 |
| 文件大?。?/td> | 363K |
| 代理商： | HDMP-1024 |
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word data at the data inputs. If
neither CAV* nor DAV* is set low,
then the transmitter assumes the
link is not being used. In this
state, the control logic triggers
the Data Encoder to send Fill
Frames to maintain the link DC
balance and allow the receiver to
maintain frequency and phase
lock. The type of fill frames sent
(FF0 or FF1) is determined by the
FF input. In a duplex system, FF
is normally connected to the Rx’s
STAT1 pin.
The C-Field Encoder, based on
the inputs at DAV*, CAV*,
FLAGSEL, and FLAG, supplies
four encoded bits to the frame
mux. This encoded data contains
the master transition (which the
receiver uses for frequency
locking), as well as information
regarding the data type: control,
data, or fill frame. In order for the
FLAG bit to be used as an
additional data bit, FLAGSEL
must be set high for both the Tx
and the Rx.
D-Field Encoder
The D-Field Encoder provides the
remaining parallel word data to
the frame mux. Based on control
signals from the Control Logic,
the D-Field Encoder either
outputs the parallel information at
its data inputs (D0..D19) or the
designated Fill Frame. RST*,
when set low, resets the internal
chip registers.
Frame Mux
The Frame Mux accepts the
output from the C-Field and D-
Field Encoders. The four control
bits are attached to the data bits,
either 16 or 20 data bits based on
the M20SEL input. This parallel
information, now either 20 or 24
bits wide, is multiplexed to a
serial line based on the internal
high speed serial clock.
SIGN
The sign circuitry determines the
cumulative sign of the outgoing
data frame, containing the data
and control bits. This is used by
the accumulator/inverter to
maintain DC balance for the
transmission line.
Accumulator/Invert
The Accumulator/Invert block is
responsible for maintaining the
DC balance of the serial line. It
determines, based on history and
the sign of the current data frame,
whether or not the current frame
should be inverted to bring the
line closer to the desired 50%
duty cycle. INV is set high when
the data frame is inverted.
Output Select
In normal operation, the serial
data stream is placed at DOUT.
By asserting LOOPEN, the user
may also direct the serial data
stream to LOUT, which may be
used for loopback testing. When
LOOPEN is not asserted, LOUT is
disabled to reduce power
consumption.
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| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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