參數(shù)資料
型號(hào)： GS4911BCNE3
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁數(shù)： 98/113頁
文件大?。?/td> 1017K
代理商： GS4911BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
98 of 113
56h
2
V_Sync - set this bit HIGH to invert the polarity of the V
Sync timing output signal.
By default, the V Sync signal is active LOW.
Reference:
Table 1-3
R/W
0
56h
1
H_Blanking - set this bit HIGH to invert the polarity of
the H Blanking timing output signal.
By default, the H Blanking signal will be LOW for the
portion of the video line containing valid video samples.
Reference:
Table 1-3
R/W
0
56h
0
H_Sync - set this bit HIGH to invert the polarity of the H
Sync timing output signal.
By default, the H Sync signal is active LOW.
Reference:
Table 1-3
R/W
0
H_Start_1
57h
15-0
The value programmed in this register indicates the
pixel start point for the leading edge of the
user-programmed H Sync signal USER1_H.
NOTE: The value programmed in this register must be
less than the value programmed in H_Stop_1.
Reference:
Section 3.8.3 on page 69
R/W
0
H_Stop_1
58h
15-0
The value programmed in this register indicates the
pixel end point for the trailing edge of the
user-programmed H Sync signal USER1_H.
NOTE: The value programmed in this register must not
exceed the maximum number of clock periods per line
of the outgoing standard.
Reference:
Section 3.8.3 on page 69
R/W
0
V_Start_1
59h
15
Reserved. Set this bit to zero when writing to 59h.
–
–
59h
14-0
The value programmed in this register indicates the start
line number of the leading edge of the
user-programmed V Sync signal USER1_V. For
interlaced output standards, this value corresponds to
the odd field number.
NOTE: The value programmed in this register must be
less than the value programmed in V_Stop_1.
Reference:
Section 3.8.3 on page 69
R/W
0
V_Stop_1
5Ah
15
Reserved. Set this bit to zero when writing to 5Ah.
–
–
5Ah
14-0
The value programmed in this register indicates the end
line number of the trailing edge of the user-programmed
V Sync signal USER1_V. For interlaced output
standards, this value corresponds to the odd field
number.
NOTE: The value programmed in this register must not
exceed the maximum number of lines per field of the
outgoing standard.
Reference:
Section 3.8.3 on page 69
R/W
0
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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