參數(shù)資料
型號： GS4911BCNE3
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標清/圖形時鐘和定時發(fā)生器鎖相
文件頁數(shù)： 38/113頁
文件大?。?/td> 1017K
代理商： GS4911BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
38 of 113
V_Offset (1Ch) - the difference between the reference VSYNC signal and the
output V Sync and/or V Blanking in lines, with a control range of zero to +1
frame. All line-based timing output signals will be delayed by the vertical offset
programmed in this register.
The encoding scheme for the Clock_Phase_Offset register (1Dh) is shown in
Table 3-1
. The offset programmed will be in the positive direction. Note that the
step size will depend on the frequency of the output video clock.
NOTE: If VID_STD[5:0] = 63 and the reference format is changed, care must be
taken to ensure that the Clock_Phase_Offset register is correctly programmed for
the new output format
before
the reference is applied.
The value programmed in the H_Offset register (1Bh) must not exceed the
maximum number of clock periods per line of the outgoing video standard.
Similarly, the value programmed in the V_Offset register (1Ch) must not exceed
the maximum number of lines per frame of the outgoing standard. Both horizontal
and vertical offsets will be in the positive direction. Negative offsets (advances) are
achieved by programming a value in the appropriate register equal to the maximum
allowable offset minus the desired advance.
NOTES:
1. The device will delay all output timing signals by 2 PCLKs relative to the input
HSYNC reference. This will occur even when the H_Offset register is not
programmed. The user may compensate for this delay by subtracting 2 PCLK
cycles from the desired horizontal offset before loading the value into the host
interface.
Table 3-1: Clock_Phase_Offset[15:0] Encoding Scheme
VID_STD[5:0]
Setting
Output Video Clock
Frequency
Step Size
(Fraction
of a
PCLK)
Maximum
Number of
Steps
Bits Required to
Set the Number
of Steps
Clock_Phase_Offset
[15:0] Settings
1
f
PCLK
< 20MHz
511
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
b
8
000001b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
3-6, 39-42
20MHz < f
PCLK
< 40MHz
255
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
b
7
000010b
7
b
6
b
5
b
4
0b
3
b
2
b
1
b
0
7-20, 25-38, 43-46
40MHz < f
PCLK
< 80MHz
127
b
6
b
5
b
4
b
3
b
2
b
1
b
0
b
6
000100b
6
b
5
b
4
00b
3
b
2
b
1
b
0
21-23, 47-51
f
PCLK
> 80MHz
63
b
5
b
4
b
3
b
2
b
1
b
0
b
5
001000b
5
b
4
000b
3
b
2
b
1
b
0
Note: Program Clock_Phase_Offset = 0000 0000 0000 0000b to achieve a zero clock phase offset.
512
---1
256
---1
128
---1
1
64
-----
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