參數(shù)資料
型號(hào)： GS4911BCNE3
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 60/113頁(yè)
文件大?。?/td> 1017K
代理商： GS4911BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
60 of 113
3.6.4.2 Loop Bandwidth of the Audio PLL (GS4911B only)
The capacitive component of the filter controlling the audio loop bandwidth is
determined by the Audio_Cap_Genlock register and the resistive component is
determined by the Audio_Res_Genlock register. These two registers are located
at addresses 39h and 3Ah, respectively, of the host interface.
To determine the setting of Audio_Res_Genlock and Audio_Cap_Genlock, the
following equations must be solved:
where:
BW = the desired audio PLL loop bandwidth
JITTERIN = Jitter present on output PCLK, in seconds.
A_Feedback_Divide = the numerator of the audio PLL divide ratio
A_Feedback_Divide is calculated in the same way as demonstrated in
Section 3.6.2.2 on page 56.
NOTE: The bandwidth calculation represented by the above equation is only
approximate. As the programmed value of Audio_Res_Genlock becomes larger,
the approximation becomes more accurate.
NOTE2: The value programmed in the Audio_Res_Genlock register must be
between 32 and 42. The value programmed in the Audio_Cap_Genlock register
must be greater than 10. These limits define the exact range of loop bandwidth
adjustment available.
3.6.5 Locking to Digital Timing from a Deserializer
As described in
Section 3.4.1 on page 43
, the GS4911B/GS4910B may be
genlocked to either an analog reference, such as a Black & Burst signal, or to an
SDI input via the digital H, V, and F blanking signals normally produced by a
deserializer. When locking to an SDI input, the user should consider the possibility
of a switch of the SDI signal upstream from the system.
If the GS4911B/GS4910B is locked to the digital H, V, and F blanking signals
produced by a deserializer, and the SDI input to the deserializer is switched such
that the phase of the H input changes abruptly, the REF_LOST output will remain
LOW and the GS4911B/GS4910B will not crash lock to the new H phase. Instead,
the clock and timing outputs will very slowly drift towards the new phase. During
this period of drift, the LOCK_LOST output will be LOW, even though the device is
not genlocked.
The user should clear the Run_Window bits [2:0] of register adress 24h to force the
device to crash lock should such a switch occur. This will cause the
Audio_Res_Genlock
47
log
2
6
BW
JITTERIN
A _Feedback_Divide
×
×
×
(
)
+
=
Audio_Cap_Genlock
Audio_Res_Genlock
21
–
≤
相關(guān)PDF資料
PDF描述
GS4915 CONN,S/R,8 POS,254C-08-1, CLOSED END STRAIN RELIEF COVER
GS6332 3 Pin, Low-Power, P Reset Circuits
GS6332UR15D1 3 Pin, Low-Power, P Reset Circuits
GS6333UR19D1 FC/ACP F.O. SINGLE MODE IN-LINE ATTENUATOR 10DB
GS6332UR19D1 FC/PC F.O. SINGLE MODE IN-LINE ATTENUATOR 5 DB
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS4915 制造商:GENNUM 制造商全稱(chēng):GENNUM 功能描述:ClockCleaner
GS4915_09 制造商:GENNUM 制造商全稱(chēng):GENNUM 功能描述:ClockCleaner
GS4915-CNE3 制造商:Semtech Corporation 功能描述:QFN-40 pin (490/tray)
GS4915INE3 制造商:Gennum Corporation 功能描述:CLOCKCLEANER HD/SD VIDEO INPUT 40QFN 制造商:Gennum Corporation 功能描述:CLOCKCLEANER, HD/SD, VIDEO INPUT, 40QFN
GS4915-INE3 功能描述:IC CLK JITTER CLEANR 40QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:ClockCleaner™ 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類(lèi)型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤(pán)，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱(chēng):SY58052UMGTRSY58052UMGTR-ND
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*