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參數(shù)資料
| 型號： | GS4911BCNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| 中文描述： | 高清/標(biāo)清/圖形時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 10/113頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | GS4911BCNE3 |
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GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
10 of 113
1.3 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name
Timing
Type
Description
1
LOCK_LOST
Non
Synchronous
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be HIGH if the output is not genlocked to the input.
The GS4911B/GS4910B monitors the output pixel/line counters, as well
as the internal lock status from the genlock block and asserts
LOCK_LOST HIGH if it is determined that the output is not genlocked to
the input. This pin will be LOW if the device successfully genlocks the
output clock and timing signals to the input reference.
If LOCK_LOST is LOW, the reference timing generator outputs will be
phase locked to the detected reference signal, producing an output in
accordance with the video standard selected by the VID_STD[5:0] pins.
2
REF_LOST
Non
Synchronous
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be HIGH if:
No input reference signal is applied to the device; or
The input reference applied does not meet the minimum/maximum
timing requirements described in
Section 3.5.2 on page 45
.
This pin will be LOW otherwise.
If the reference signal is removed when the device is in Genlock mode,
REF_LOST will go HIGH and the GS4911B/GS4910B will enter Freeze
mode (see
Section 3.2.1.2 on page 40
).
3
VID_PLL_VDD
–
Power
Supply
Most positive power supply connection for the video clock synthesis
internal block. Connect to +1.8V DC.
4
VID_PLL_GND
–
Power
Supply
Ground connection for the video clock synthesis internal block. Connect
to GND.
5
XTAL_VDD
–
Power
Supply
Most positive power supply connection for the crystal buffer. Connect to
either +1.8V DC or +3.3V DC.
NOTE: Connect to +3.3V for minimum output PCLK jitter.
6
X1
Non
Synchronous
Input
ANALOG SIGNAL INPUT
Connect to a 27MHz crystal or a 27MHz external clock source. See
Figure 1-1
.
7
X2
Non
Synchronous
Output
ANALOG SIGNAL OUTPUT
Connect to a 27MHz crystal, or leave this pin open circuit if an external
clock source is applied to pin 6. See
Figure 1-1
.
8
XTAL_GND
–
Power
Supply
Ground connection for the crystal buffer. Connect to GND.
9
CORE_GND
–
Power
Supply
Ground connection for core and I/O. Solder to the ground plane of the
application board.
NOTE: The CORE_GND pin should be soldered to the same main
ground plane as the exposed ground pad on the bottom of the device.
10
ANALOG_VDD
–
Power
Supply
Most positive power supply connection for the analog input block.
Connect to +1.8V DC.
11, 20, 63
NC
–
–
Do not connect.
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| GS4915-INE3 | 功能描述:IC CLK JITTER CLEANR 40QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:ClockCleaner™ 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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