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| 型號： | GS4911BCNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| 中文描述： | 高清/標(biāo)清/圖形時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 11/113頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | GS4911BCNE3 |
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GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
11 of 113
12
ANALOG_GND
–
Power
Supply
Ground connection for the analog input block. Connect to GND.
13
AUD_PLL_GND
(GS4911B only)
–
Power
Supply
Ground connection for the audio clock synthesis internal block. Connect
to GND.
ANALOG_GND
(GS4910B only)
–
Power
Supply
Ground connection for the analog input block. Connect to GND.
14
AUD_PLL_VDD
(GS4911B only)
–
Power
Supply
Most positive power supply connection for the audio clock synthesis
internal block. Connect to +1.8V DC.
ANALOG_GND
(GS4910B only)
–
Power
Supply
Ground connection for the analog input block. Connect to GND.
15
10FID
Non
Synchronous
Input
REFERENCE SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
The 10FID external reference signal is applied to this pin by the
application layer. 10FID defines the field in which the video and audio
clock phase relationship is defined according to SMPTE 318-M. It is also
used to define a 3:2 video cadence.
NOTE: If the input reference format does not include a 10 Field ID signal,
this pin should be held LOW. See
Section 3.4.2 on page 44
.
16
HSYNC
Non
Synchronous
Input
REFERENCE SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
The HSYNC external reference signal is applied to this pin by the
application layer. When the GS4911B/GS4910B is operating in Genlock
mode, the device senses the polarity of the HSYNC input automatically,
and references to the leading edge.
If the user wishes to select one of the pre-programmed video and/or
timing output signals provided by the device, then this signal must
adhere to one of the 36 defined video or 16 different graphics display
standards supported by the device. In this mode of operation, the
HSYNC input provides a horizontal scanning reference signal.
The HSYNC signal may have analog timing, such as from a sync
separator, or may be digital such as from an SDI deserializer.
Section 1.4
on page 20
describes the 36 video formats and 16 graphic formats
recognized by the GS4911B/GS4910B.
17
VSYNC
Non
Synchronous
Input
REFERENCE SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
The VSYNC external reference signal is applied to this pin by the
application layer. When the GS4911B/GS4910B is operating in Genlock
mode, the device senses the polarity of the VSYNC input automatically,
and references to the leading edge.
If the user wishes to select one of the pre-programmed video and/or
timing output signals provided by the device, then this signal must
adhere to one of the 36 defined video or 16 different graphics display
standards supported by the device. In this mode of operation, the
VSYNC input provides a vertical scanning reference signal.
The VSYNC signal may have analog timing, such as from a sync
separator, or may be digital such as from an SDI deserializer.
Section 1.4
on page 20
describes the 36 video formats and 16 graphic formats
recognized by the GS4911B/GS4910B.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
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| GS4915 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:ClockCleaner |
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| GS4915INE3 | 制造商:Gennum Corporation 功能描述:CLOCKCLEANER HD/SD VIDEO INPUT 40QFN 制造商:Gennum Corporation 功能描述:CLOCKCLEANER, HD/SD, VIDEO INPUT, 40QFN |
| GS4915-INE3 | 功能描述:IC CLK JITTER CLEANR 40QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:ClockCleaner™ 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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