參數(shù)資料
型號(hào)： GS4911BCNE3
廠(chǎng)商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 55/113頁(yè)
文件大小： 1017K
代理商： GS4911BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
55 of 113
where:
f
out
= output video clock frequency
f
Href
= reference H pulse frequency on HSYNC
H_Feedback_Divide = numerator of the divide ratio (host register 28h-29h)
H_Reference_Divide = denominator of the divide ratio (host register 2Ah-2Bh)
Before programming H_Feedback_Divide and H_Reference_Divide, the
numerator and denominator must be reduced to their lowest factors.
For example, to manually genlock an output format with a 74.25MHz video clock to
a reference with a 27MHz video clock and 1716 clocks per line, the following
calculations are necessary:
Therefore, program H_Feedback_Divide
= 4719 and H_Reference_Divide = 1.
Output Line/Frame Reset Host Registers
In addition to programming H_Feedback_Divide and H_Reference_Divide, the
user must also define the ratio of the output frame rate to the reference frame rate.
The denominator of this ratio is programmed in the Output_FV_Reset register at
address 18h of the host interface. Before Output_FV_Reset is programmed, the
numerator and denominator must be reduced to their lowest factors. Two
examples are demonstrated below:
Example 1: the reference has a frame rate of 30Hz and the output frame rate is
50Hz:
Therefore, program Output_FV_Reset = 3. The numerator does not have to be
programmed.
Example 2: the reference has a frame rate of 29.97Hz and the output frame rate is
50Hz:
Therefore, program Output_FV_Reset = 600. The numerator does not have to be
programmed.
Additionally, the Frame_Divider_Reset register (address19h) must be configured
to initialize the counter reset programmed in register 18h.
f
Href
1716
---27
MHz
=
H_Reference_Divide
H_Feedback_Divide
MHz
1716
---27
MHz
74.25
74.25
27
1716
×
27
127413
1
4719
=
=
=
=
∴
Input Frame Rate
Output Frame Rate
30
50
5
3
=
=
Input Frame Rate
Output Frame Rate
29.97
--50
600
1001
=
=
相關(guān)PDF資料
PDF描述
GS4915 CONN,S/R,8 POS,254C-08-1, CLOSED END STRAIN RELIEF COVER
GS6332 3 Pin, Low-Power, P Reset Circuits
GS6332UR15D1 3 Pin, Low-Power, P Reset Circuits
GS6333UR19D1 FC/ACP F.O. SINGLE MODE IN-LINE ATTENUATOR 10DB
GS6332UR19D1 FC/PC F.O. SINGLE MODE IN-LINE ATTENUATOR 5 DB
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS4915 制造商:GENNUM 制造商全稱(chēng):GENNUM 功能描述:ClockCleaner
GS4915_09 制造商:GENNUM 制造商全稱(chēng):GENNUM 功能描述:ClockCleaner
GS4915-CNE3 制造商:Semtech Corporation 功能描述:QFN-40 pin (490/tray)
GS4915INE3 制造商:Gennum Corporation 功能描述:CLOCKCLEANER HD/SD VIDEO INPUT 40QFN 制造商:Gennum Corporation 功能描述:CLOCKCLEANER, HD/SD, VIDEO INPUT, 40QFN
GS4915-INE3 功能描述:IC CLK JITTER CLEANR 40QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:ClockCleaner™ 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類(lèi)型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤(pán)，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱(chēng):SY58052UMGTRSY58052UMGTR-ND
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*