參數(shù)資料
型號(hào)： GS4911BCNE3
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 59/113頁(yè)
文件大?。?/td> 1017K
代理商： GS4911BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
59 of 113
where:
BW = the desired video PLL loop bandwidth
JITTERIN = Jitter present on applied HSYNC reference signal, in seconds
H_Feedback_Divide = the numerator of the video PLL divide ratio
H_Feedback_Divide represents the numerator of the ratio of the output clock
frequency to the frequency of the H reference pulse. It is calculated as described
in
Section 3.6.2.1 on page 54
.
NOTE: The bandwidth calculation represented by the above equation is only
approximate. As the programmed value of Video_Res_Genlock becomes larger,
the approximation becomes more accurate.
For example, the following steps are necessary to program a loop bandwidth of
25Hz given the following conditions: input HSYNC jitter = 3 ns, VID_STD[5:0] = 3
and input reference format = NTSC.
1. Calculate H_Feedback_Divide (as defined in
Section 3.6.2.1 on page 54
):
Therefore, H_Feedback_Divide = 1716.
2. Calculate the value for Video_Res_Genlock:
3. Calculate the value for Video_Cap_Genlock:
Therefore, program Video_Res_Genlock = 37 and Video_Cap_Genlock = 16.
NOTE: The value programmed in the Video_Res_Genlock register must be
between 32 and 42. The value programmed in the Video_Cap_Genlock register
must be greater than 10. These limits define the exact range of loop bandwidth
adjustment available.
H_Reference_Divide
H_Feedback_Divide
f
Hrefin
-----------------
×
f
pclkout
27
MHz
=
f
Hrefin
1716
---27
MHz
=
H_Reference_Divide
H_Feedback_Divide
27
27
1716
×
1
1716
=
=
∴
Video_Res_Genlock
47
log
2
6
25
3
10
9
–
×
(
)
×
×
1716
×
(
)
+
37
=
=
Video_Cap_Genlock
37
21
–
16
=
=
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