參數(shù)資料
型號(hào)： GS4911BCNE3
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 95/113頁(yè)
文件大?。?/td> 1017K
代理商： GS4911BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
95 of 113
RSVD
4Bh
–
Reserved.
–
–
Video_Control
4Ch
15-5
Reserved. Set these bits to zero when writing to 4Ch.
–
–
4Ch
4
10FID_F_pulse - set this bit HIGH to stretch the 10FID
pulse duration from 1 line to 1 field.
Reference:
Section 3.8.1 on page 67
R/W
0
4Ch
3-2
Reserved. Set these bits to zero when writing to 4Ch.
–
–
4Ch
1
Host_VID_STD - set this bit HIGH to select the output
video standard using register 4Dh instead of the
external VID_STD[5:0] pins.
The external VID_STD[5:0] pins will be ignored, but
should not be left floating.
Reference:
Section 1.4 on page 20
R/W
0
4Ch
0
Reserved. Set this bit to zero when writing to 4Ch.
–
–
VID_STD[5:0]
4Dh
15-6
Reserved. Set these bits to zero when writing to 4Dh.
–
–
4Dh
5-0
Replaces the external VID_STD[5:0] pins when
VID_From_Host (bit 1 of address 4Ch) is HIGH.
Reference:
Section 1.4 on page 20
R/W
00h
Clocks_Per_Line
4Eh
15-0
Contains the number of output video clock cycles per
line for the selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
Section 3.10 on page 74
R/W
–
Clocks_Per_Hsync
4Fh
15-0
Contains the number of output video clock cycles in the
active H Sync interval for the selected output timing
format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
Section 3.10 on page 74
R/W
–
Hsync_To_SAV
50h
15-0
Contains the number of output video clock cycles from
the start of H Sync to the start of active video for the
selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
Section 3.10 on page 74
R/W
–
Hsync_To_EAV
51h
15-0
Contains the number of output video clock cycles from
the start of H Sync to the end of active video for the
selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
Section 3.10 on page 74
R/W
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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