參數(shù)資料
型號: GS4911BCNE3
廠商: Gennum Corporation
英文描述: HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述: 高清/標(biāo)清/圖形時鐘和定時發(fā)生器鎖相
文件頁數(shù): 39/113頁
文件大?。?/td> 1017K
代理商: GS4911BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
39 of 113
2. For both sync and blanking-based input references, the device will advance all
line-based output timing signals by 1 line relative to the input VSYNC
reference for all output standards except VID_STD[5:0] = 4, 6, and 8. This will
occur even when the V_Offset register is not programmed. The user may
compensate for this advance by adding 1 line to the desired vertical offset
before loading this value into the register.
3. When locking the "
f/1.001
" HD output standards to the 525-line SD input
reference standards, or vice versa, the device will delay all line-based output
timing signals by
Δ
VSync lines relative to the input VSYNC reference. This will
occur even when the V_Offset register is not programmed. The user may
compensate for this delay by subtracting
Δ
VSync lines from the desired
vertical offset before loading this value into the register.
The value
Δ
VSync is given by the equation:
where:
HSYNC_IN_Period = the period of the H reference pulse
Δ
VSYNC_HSYNC = the time difference between the leading edges of the
applied V and H reference pulses
Hsync_OUT_Period = the period of the generated H Sync output
See
Figure 3-1
. H_Feedback_Divide represents the numerator of the ratio of
the output clock frequency to the frequency of the H reference pulse. It is
calculated as described in
Section 3.6.2.1 on page 54
.
Figure 3-1: HD-SD Calculation
Δ
VSync
HSYNC_IN_Period
Δ
VSYNC_HSYNC
2
(
HSYNC_OUT_Period
×
)
+
=
HSYNC
VSYNC
H Sync
V Sync
Δ
VSYNC_HSYNC
HSync_OUT_Period
HSYNC_IN_Period
Δ
VSync
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