參數(shù)資料
型號(hào)： GS4911BCNE3
廠商： Gennum Corporation
英文描述： HD/SD/Graphics Clock and Timing Generator with GENLOCK
中文描述： 高清/標(biāo)清/圖形時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 92/113頁(yè)
文件大?。?/td> 1017K
代理商： GS4911BCNE3
GS4911B/GS4910B Data Sheet
36655 - 2
April 2006
92 of 113
A_Reference_Divide
(GS4911B only)
3Eh-3Dh
31-0
In the internal audio genlock block, this register defines
the denominator of the divide ratio.
This register may be programmed to manually genlock
the audio clock to the video clock.
The default value of this register will vary depending on
the output video standard selected.
Address 3Dh = bits 15-0
Address 3Eh = bits 31-16
Reference:
Section 3.6.2.2 on page 56
R/W
–
ACLK1_fs_Multiple
(GS4911B only)
3Fh
15-3
Reserved. Set these bits to zero when writing to 3Fh.
–
–
3Fh
2-0
The user may set this register to select the desired
frequency of the audio clock on ACLK1 (a multiple of the
fundamental sampling rate, fs). The audio clock
frequency may be set as: 512fs, 384fs, 256fs, 192fs,
128fs, 64fs, fs, or z-bit. See
Table 3-8
for more details.
NOTE: To output a frequency of 348fs or 192fs, bit 5 of
register 31h must also be set HIGH.
Reference:
Section 3.7.2 on page 63
R/W
0
ACLK2_fs_Multiple
(GS4911B only)
40h
15-3
Reserved. Set these bits to zero when writing to 40h.
–
–
40h
2-0
The user may set this register to select the desired
frequency of the audio clock on ACLK2 (a multiple of the
fundamental sampling rate, fs). The audio clock
frequency may be set as: 512fs, 384fs, 256fs, 192fs,
128fs, 64fs, fs, or z-bit. See
Table 3-8
for more details.
NOTE: To output a frequency of 348fs or 192fs, bit 5 of
register 31h must also be set HIGH.
Reference:
Section 3.7.2 on page 63
R/W
0
ACLK3_fs_Multiple
(GS4911B only)
41h
15-3
Reserved. Set these bits to zero when writing to 41h.
–
–
41h
2-0
The user may set this register to select the desired
frequency of the audio clock on ACLK3 (a multiple of the
fundamental sampling rate, fs). The audio clock
frequency may be set as: 512fs, 384fs, 256fs, 192fs,
128fs, 64fs, fs, or z-bit. See
Table 3-8
for more details.
NOTE: To output a frequency of 348fs or 192fs, bit 5 of
register 31h must also be set HIGH.
Reference:
Section 3.7.2 on page 63
R/W
0
RSVD
42h
–
Reserved.
–
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
相關(guān)PDF資料
PDF描述
GS4915 CONN,S/R,8 POS,254C-08-1, CLOSED END STRAIN RELIEF COVER
GS6332 3 Pin, Low-Power, P Reset Circuits
GS6332UR15D1 3 Pin, Low-Power, P Reset Circuits
GS6333UR19D1 FC/ACP F.O. SINGLE MODE IN-LINE ATTENUATOR 10DB
GS6332UR19D1 FC/PC F.O. SINGLE MODE IN-LINE ATTENUATOR 5 DB
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS4915 制造商:GENNUM 制造商全稱(chēng):GENNUM 功能描述:ClockCleaner
GS4915_09 制造商:GENNUM 制造商全稱(chēng):GENNUM 功能描述:ClockCleaner
GS4915-CNE3 制造商:Semtech Corporation 功能描述:QFN-40 pin (490/tray)
GS4915INE3 制造商:Gennum Corporation 功能描述:CLOCKCLEANER HD/SD VIDEO INPUT 40QFN 制造商:Gennum Corporation 功能描述:CLOCKCLEANER, HD/SD, VIDEO INPUT, 40QFN
GS4915-INE3 功能描述:IC CLK JITTER CLEANR 40QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:ClockCleaner™ 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類(lèi)型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤(pán)，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱(chēng):SY58052UMGTRSY58052UMGTR-ND
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*