參數(shù)資料
型號(hào): DS21554LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 85/117頁
文件大?。?/td> 698K
代理商: DS21554LN
DS21354 & DS21554
7 of 117
3 INTRODUCTION
The DS21354/554 is a superset version of the popular DS2153 and DS2154 SCTs offering the new
features listed below. All of the original features of the DS2153 and DS2154 have been retained and
software created for the original devices is transferable into the DS21354/554.
New Features in the DS21354 and DS21554
FEATURE
SECTION
HDLC controller with 64-byte buffers for Sa bits or DS0s or sub DS0s
15
Interleaving PCM bus operation
18
IEEE 1149.1 JTAG-Boundary Scan Architecture
17
3.3V (DS21354 only) supply
2 and 3
Line Interface Support for the G.703 2.048 Synchronization Interface
16
Customer Disconnect Indication (...101010...) Generator
6
Open Drain Line Driver Option
16
New Features in the DS2154 (also in the DS21354 and DS21554)
FEATURE
SECTION
Option for non–multiplexed bus operation
1 and 2
Crystal–less jitter attenuation
12
Additional hardware signaling capability including:
Receive signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing Interrupt generated on change of signaling data
7
Improved receive sensitivity: 0 dB to –43 dB
12
Per–channel code insertion in both transmit and receive paths
8
Expanded access to Sa and Si bits
11
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state
4
8.192 MHz clock synthesizer
1
Per–channel loopback
8
Addition of hardware pins to indicate carrier loss and signaling freeze
1
Line interface function can be completely decoupled from the framer/formatter to
allow:
Interface to optical, HDSL, and other NRZ interfaces
“tap” the transmit and receive bipolar data streams for monitoring purposes
Be able to corrupt data and insert framing errors, CRC errors, etc.
1
Transmit and receive elastic stores now have independent backplane clocks
1
Ability to monitor one DS0 channel in both the transmit and receive paths
6
Access to the data streams in between the framer/formatter and the elastic stores
1
AIS generation in the line interface that is independent of loopbacks
1 and 3
Transmit current limiter to meet the 50 mA short circuit requirement
12
Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233
3
Automatic RAI generation to ETS 300 011 specifications
3
相關(guān)PDF資料
PDF描述
DS2155G DATACOM, FRAMER, PBGA100
DS21600SN PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
DS21600N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
DS2155LN DATACOM, FRAMER, PQFP100
DS21602N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
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