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參數(shù)資料
| 型號(hào)： | DS21554LN |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Interface |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 14 MM, LQFP-100 |
| 文件頁(yè)數(shù)： | 70/117頁(yè) |
| 文件大小： | 698K |
| 代理商： | DS21554LN |
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DS21354 & DS21554
56 of 117
13 ELASTIC STORES OPERATION
The DS21354/554 contains dual two–frame (512 bits) elastic stores, one for the receive direction, and one
for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate
convert the E1 data stream to 1.544 Mbps (or a multiple of 1.544 Mbps) which is the T1 rate. Secondly,
they can be used to absorb the differences in frequency and phase between the E1 data stream and an
asynchronous (i.e., not frequency locked) backplane clock which can be 1.544 MHz or 2.048/4.096/8.192
MHz. The backplane clock can burst at rates up to 8.192 MHz. Both elastic stores contain full controlled
slip capability which is necessary for this second purpose. The elastic stores can be forced to a known
depth via the Elastic Store Reset bits (CCR6.0 & CCR6.1). Toggling these bits forces the read and write
pointers into opposite frames. Both elastic stores within a framer are fully independent and no restrictions
apply to the sourcing of the various clocks that are applied to them. The transmit side elastic store can be
enabled whether the receive elastic store is enabled or disabled and vice versa. Also, each elastic store can
interface to either a 1.544 MHz or 2.048/4.096/8.192 MHz backplane without regard to the backplane rate
the other elastic store is interfacing.
13.1 Receive Side
If the receive side elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544 MHz
(RCR2.2 =0) or 2.048/4.096/8.192 MHz (RCR2.2 = 1) clock at the RSYSCLK pin. The user has the
option of either providing a frame/multiframe sync at the RSYNC pin (RCR1.5 = 1) or having the
RSYNC pin provide a pulse on frame/multiframe boundaries (RCR1.5 = 0). If the user wishes to obtain
pulses at the frame boundary, then RCR1.6 must be set to zero and if the user wishes to have pulses occur
at the multiframe boundary, then RCR1.6 must be set to one. The DS21354/554 will always indicate
frame boundaries via the RFSYNC output whether the elastic store is enabled or not. If the elastic store is
enabled, then either CAS (RCR1.7 = 0) or CRC4 (RCR1.7 = 1) multiframe boundaries will be indicated
via the RMSYNC output. If the user selects to apply a 1.544 MHz clock to the RSYSCLK pin, then every
fourth channel of the received E1 data will be deleted and a F–bit position (which will be forced to one)
will be inserted. Hence Channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28)
will be deleted from the received E1 data stream. Also, in 1.544 MHz applications, the RCHBLK output
will not be active in Channels 25 through 32 (or in other words, RCBR4 is not active). See Section 19.1
for timing details. If the 512–bit elastic buffer either fills or empties, a controlled slip will occur. If the
buffer empties, then a full frame of data (256–bits) will be repeated at RSER and the SR1.4 and RIR.3
bits will be set to a one. If the buffer fills, then a full frame of data will be deleted and the SR1.4 and
RIR.4 bits will be set to a one.
13.2 Transmit Side
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR3.7. A 1.544 MHz (CCR3.1 = 0) or 2.048/4.096/8.192 MHz (CCR3.1 = 1) clock
can be applied to the TSYSCLK input. The TSYSCLK can be a bursty clock with rates up to 8.192 MHz.
The user must supply either an 8 kHz frame sync pulse or a multiframe sync pulse to the TSSYNC input.
See Section 19.2 for timing details. Controlled slips in the transmit elastic store are reported in the SR2.0
bit and the direction of the slip is reported in the RIR.6 and RIR.7 bits.
14 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
The DS21354/554 provides for access to both the Sa and the Si bits via three different methods. The first
is via a hardware scheme using the RLINK/RLCLK and TLINK/ TLCLK pins. The first method is
discussed in Section 14.1. The second involves using the internal RAF/RNAF and TAF/TNAF registers
and is discussed in Section 14.2 The third method which is covered in Section 14.3 involves an expanded
version of the second method and is one of the features added to the DS2154/354/554 from the original
DS2153 definition.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2155G | DATACOM, FRAMER, PBGA100 |
| DS21600SN | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| DS21600N | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8 |
| DS2155LN | DATACOM, FRAMER, PQFP100 |
| DS21602N | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21554LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2155DK | 功能描述:網(wǎng)絡(luò)開(kāi)發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS2155G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1/E1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2155G/T&R | 制造商:Maxim Integrated Products 功能描述:DS2155 T1/E1/J1 SCT 100P CSBGA T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC LIU T1/E1/J1 SCT 100P CSBGA 制造商:Maxim Integrated Products 功能描述:Network Controller & Processor ICs T1/E1/J1 Transceiver |
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