參數(shù)資料
型號: DS21554LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 54/117頁
文件大小: 698K
代理商: DS21554LN
DS21354 & DS21554
41 of 117
SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)
(MSB)
(LSB)
CSC5
CSC4
CSC3
CSC2
CSC0
FASSA
CASSA
CRC4SA
SYMBOL
POSITION NAME AND DESCRIPTION
CSC5
SSR.7
CRC4 Sync Counter Bit 5. MSB of the 6–bit counter.
CSC4
SSR.6
CRC4 Sync Counter Bit 4.
CSC3
SSR.5
CRC4 Sync Counter Bit 3.
CSC2
SSR.4
CRC4 Sync Counter Bit 2.
CSC0
SSR.3
CRC4 Sync Counter Bit 0. LSB of the 6–bit counter. The next to LSB
is not accessible.
FASSA
SSR.2
FAS Sync Active. Set while the synchronizer is searching for alignment
at the FAS level.
CASSA
SSR.1
CAS MF Sync Active. Set while the synchronizer is searching for the
CAS MF alignment word.
CRC4SA
SSR.0
CRC4 MF Sync Active. Set while the synchronizer is searching for the
CRC4 MF alignment word.
7.1 CRC4 Sync Counter
The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out. The counter
is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can
also be cleared by disabling the CRC4 mode (CCR1.0=0). This counter is useful for determining the
amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests
that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search should be
abandoned and proper action taken. The CRC4 Sync Counter will rollover.
SR1: STATUS REGISTER 1 (Address=06 Hex)
(MSB)
(LSB)
RSA1
RDMA
RSA0
RSLIP
RUA1
RRA
RCL
RLOS
SYMBOL
POSITION NAME AND DESCRIPTION
RSA1
SR1.7
Receive Signaling All Ones / Signaling Change. Set when the contents
of timeslot 16 contains less than three zeros over 16 consecutive frames.
This alarm is not disabled in the CCS signaling mode. Both RSA1 and
RSA0 will be set if a change in signaling is detected.
RDMA
SR1.6
Receive Distant MF Alarm. Set when bit–6 of timeslot 16 in frame 0
has been set for two consecutive multiframes. This alarm is not disabled
in the CCS signaling mode.
RSA0
SR1.5
Receive Signaling All Zeros / Signaling Change. Set when over a full
MF, timeslot 16 contains all zeros. Both RSA1 and RSA0 will be set if a
change in signaling is detected.
RSLIP
SR1.4
Receive Side Elastic Store Slip. Set when the elastic store has either
repeated or deleted a frame of data.
RUA1
SR1.3
Receive Unframed All Ones. Set when an unframed all ones code is
received at RPOSI and RNEGI.
RRA
SR1.2
Receive Remote Alarm. Set when a remote alarm is received at RPOSI
and RNEGI.
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