參數(shù)資料
型號: DS21554LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 83/117頁
文件大?。?/td> 698K
代理商: DS21554LN
DS21354 & DS21554
68 of 117
SYMBOL
POSITION NAME AND DESCRIPTION
TDS0M
TDC1.5
DS0 Selection Mode.
0 = utilize the TD0 to TD4 bits to select which single DS0 channel to use.
1 = utilize the TCHBLK control registers to select which DS0 channels to
use.
TD4
TDC1.4
DS0 Channel Select Bit 4. MSB of the DS0 channel select.
TD3
TDC1.3
DS0 Channel Select Bit 3.
TD2
TDC1.2
DS0 Channel Select Bit 2.
TD1
TDC1.1
DS0 Channel Select Bit 1.
TD0
TDC1.0
DS0 Channel Select Bit 0. LSB of the DS0 channel select.
TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address=BB Hex)
(MSB)
(LSB)
TDB8
TDB7
TDB6
TDB5
TDB4
TDB3
TDB2
TDB1
SYMBOL
POSITION NAME AND DESCRIPTION
TDB8
TDC2.7
DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop this bit
from being used.
TDB7
TDC2.6
DS0 Bit 7 Suppress Enable. Set to one to stop this bit from being used.
TDB6
TDC2.5
DS0 Bit 6 Suppress Enable. Set to one to stop this bit from being used.
TDB5
TDC2.4
DS0 Bit 5 Suppress Enable. Set to one to stop this bit from being used.
TDB4
TDC2.3
DS0 Bit 4 Suppress Enable. Set to one to stop this bit from being used.
TDB3
TDC2.2
DS0 Bit 3 Suppress Enable. Set to one to stop this bit from being used.
TDB2
TDC2.1
DS0 Bit 2 Suppress Enable. Set to one to stop this bit from being used.
TDB1
TDC2.0
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop this bit
from being used.
16 LINE INTERFACE FUNCTIONS
The line interface function in the DS21354/554 contains three sections; (1) the receiver which handles
clock and data recovery, (2) the transmitter which waveshapes and drives the E1 line, and (3) the jitter
attenuator. Each of the these three sections is controlled by the Line Interface Control Register (LICR)
which is described below.
LICR: LINE INTERFACE CONTROL REGISTER (Address=18 Hex)
(MSB)
(LSB)
L2
L1
L0
EGL
JAS
JABDS
DJA
TPD
SYMBOL
POSITION NAME AND DESCRIPTION
L2
LICR.7
Line Build Out Select Bit 2. Sets the transmitter build out; see Table 16-
1 and Table 16-2.
L1
LICR.6
Line Build Out Select Bit 1. Sets the transmitter build out; see Table 16-
1 and Table 16-2.
L0
LICR.5
Line Build Out Select Bit 0. Sets the transmitter build out; see Table 16-
1 and Table 16-2.
EGL
LICR.4
Receive Equalizer Gain Limit.
0 = –12 dB
1 = –43 dB
相關(guān)PDF資料
PDF描述
DS2155G DATACOM, FRAMER, PBGA100
DS21600SN PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
DS21600N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
DS2155LN DATACOM, FRAMER, PQFP100
DS21602N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
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