參數資料
型號: DS21554LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數: 14/117頁
文件大?。?/td> 698K
代理商: DS21554LN
DS21354 & DS21554
110 of 117
21.3 Receive Side AC Characteristics
AC CHARACTERISTICS – RECEIVE SIDE [See Figure 21-8 to Figure 21-10]
(0
°°°°C to 70°°°°C; VDD = 3.3V ±±±± 5% for DS21354L;
0
°°°°C to 70°°°°C; VDD = 5.0V ±±±± 5% for DS21554L;
-40
°°°°C to +85°°°°C; VDD = 3.3V ±±±± 5% for DS21354LN;
-40
°°°°C to +85°°°°C; VDD = 5.0V ±±±± 5% for DS21554LN)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
RCLKO Period
tLP
488
ns
RCLKO Pulse Width
tLH
tLL
200
244
ns
1
RCLKO Pulse Width
tLH
tLL
150
244
ns
2
RCLKI Period
tCP
488
ns
RCLKI Pulse Width
tCH
tCL
75
ns
RSYSCLK Period
tSP
100
648
488
244
122
ns
3
4
5
6
RSYSCLK Pulse Width
tSH
tSL
50
ns
RSYNC Set Up to RSYSCLK Falling
tSU
20
tSH –5
ns
RSYNC Pulse Width
tPW
50
ns
RPOSI/RNEGI Set Up to RCLKI
Falling
tSU
20
ns
RPOSI/RNEGI Hold From RCLKI
Falling
tHD
20
ns
RSYSCLK/RCLKI Rise and Fall Times
tR, tF
25
ns
Delay RCLKO to RPOSO, RNEGO
Valid
tDD
50
ns
Delay RCLK to RSER, RDATA, RSIG,
RLINK Valid
tD1
50
ns
Delay RCLK to RCHCLK, RSYNC,
RCHBLK, RFSYNC, RLCLK
tD2
50
ns
Delay RSYSCLK to RSER, RSIG Valid
tD3
50
ns
Delay RSYSCLK to RCHCLK,
RCHBLK, RMSYNC, RSYNC, CO
tD4
50
ns
CI Set Up to RSYSCLK Rising
tSC
20
ns
CI Pulse Width
tWC
50
ns
NOTES:
1. Jitter attenuator enabled in the receive path.
2. Jitter attenuator disabled or enabled in the transmit path.
3. RSYSCLK = 1.544 MHz.
4. RSYSCLK = 2.048 MHz.
5. RSYSCLK = 4.096 MHz
6. RSYSCLK = 8.192 MHz
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