參數(shù)資料
型號： DS21554LN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Interface
英文描述： DATACOM, PCM TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, LQFP-100
文件頁數(shù)： 77/117頁
文件大?。?/td> 698K
代理商： DS21554LN
DS21354 & DS21554
62 of 117
Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware
interrupt via the INT* output pin. Each of the events in the HSR can be either masked or unmasked from
the interrupt pin via the HDLC Interrupt Mask Register (HIMR). Interrupts will force the INT* pin low
when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present)
when the user reads the event bit that caused the interrupt to occur.
15.3 Basic Operation Details
As a basic guideline for interpreting and sending HDLC messages, the following sequences can be
applied:
15.3.1 Receive a HDLC Message
1. enable RPS interrupts
2. wait for interrupt to occur
3. disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt
4. read RHIR to obtain REMPTY status
a. if REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO
a1. if CBYTE=0 then skip to step 5
a2. if CBYTE=1 then skip to step 7
b. if REMPTY=1, then skip to step 6
5. repeat step 4
6. wait for interrupt, skip to step 4
7. if POK=0, then discard whole packet, if POK=1, accept the packet
a. disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.
15.3.2 Transmit an HDLC Message
1. make sure HDLC controller is done sending any previous messages and is current sending flags by
checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register
2. enable either the THALF or TNF interrupt
3. read THIR to obtain TFULL status
a. if TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when
the last byte is to be written, in this case set TEOM=1 before writing the byte and then skip to
step 6)
b. if TFULL=1, then skip to step 5
4. repeat step 3
5. wait for interrupt, skip to step 3
6. disable THALF or TNF interrupt and enable TMEND interrupt
7. wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
相關(guān)PDF資料
PDF描述
DS2155G DATACOM, FRAMER, PBGA100
DS21600SN PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
DS21600N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
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