- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97866 > DS21554LN (DALLAS SEMICONDUCTOR) DATACOM, PCM TRANSCEIVER, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | DS21554LN |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Interface |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 14 MM, LQFP-100 |
| 文件頁數(shù)： | 66/117頁 |
| 文件大?。?/td> | 698K |
| 代理商： | DS21554LN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁當(dāng)前第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁
DS21354 & DS21554
52 of 117
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1
(MSB)
(LSB)
CH18
CH3
CH17
CH2
CH16
CH1
1*
TCBR1(22)
CH22
CH7
CH21
CH6
CH20
CH5
CH19
CH4
TCBR2(23)
CH26
CH11
CH25
CH10
CH24
CH9
CH23
CH8
TCBR3(24)
CH30
CH15
CH29
CH14
CH28
CH13
CH27
CH12
TCBR4(25)
* these bits should be set to one to allow the internal TS1 register to create the CAS Multiframe
Alignment Word and Spare/Remote Alarm bits.
The user can also take advantage of this functionality to intermix signaling data from the TSIG pin and
from the internal Transmit Signaling Registers (TS1 to TS16). As an example, assume that the user
wishes to source all the signaling data except for voice channels 5 and 10 from the TSIG pin. In this
application, the following bits and registers would be programmed as follows:
CONTROL BITS
REGISTER VALUES
THSE = 1 (CCR3.2)
TS1 = 0Bh (MF alignment word, remote alarm etc.)
TCBFS = 1 (CCR3.6)
TCBR1 = 03h (source timeslot 16, frame 1 data)
T16S = 0 (TCR1.5)
TCBR2 = 01h (source voice Channel 5 signaling data from TS6)
CBR3 = 04h (source voice Channel 10 signaling data from TS11)
TCBR4 = 00h
11 PER–CHANNEL CODE GENERATION AND LOOPBACK
The DS21354/554 can replace data on a channel–by–channel basis in both the transmit and receive
directions. The transmit direction is from the backplane to the E1 line and is covered in Section 11.1. The
receive direction is from the E1 line to the backplane and is covered in Section 11.2.
11.1 Transmit Side Code Generation
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the framer. The first method which is covered in Section 11.1.1 was a
feature contained in the original DS2153 while the second method which is covered in 11.1.2 is a new
feature of the DS2154/354/554.
11.1.1 Simple Idle Code Insertion and Per–Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3/4) to determine which of the 32 E1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
This method allows the same 8–bit code to be placed into any of the 32 E1 channels. If this method is
used, then the CCR3.5 control bit must be set to zero.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represent a DS0 channel
in the outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle
Code contained in the Transmit Idle Definition Register (TIDR).
The Transmit Idle Registers (TIRs) have an alternate function that allow them to define a Per–Channel
LoopBack (PCLB). If the TIRFS control bit (CCR3.5) is set to one, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the E1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2155G | DATACOM, FRAMER, PBGA100 |
| DS21600SN | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| DS21600N | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8 |
| DS2155LN | DATACOM, FRAMER, PQFP100 |
| DS21602N | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21554LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2155DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS2155G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1/E1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2155G/T&R | 制造商:Maxim Integrated Products 功能描述:DS2155 T1/E1/J1 SCT 100P CSBGA T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC LIU T1/E1/J1 SCT 100P CSBGA 制造商:Maxim Integrated Products 功能描述:Network Controller & Processor ICs T1/E1/J1 Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。