參數(shù)資料
型號(hào)： DS21554LN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Interface
英文描述： DATACOM, PCM TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, LQFP-100
文件頁數(shù)： 41/117頁
文件大?。?/td> 698K
代理商： DS21554LN
DS21354 & DS21554
3 of 117
10
SIGNALING OPERATION....................................................................................................... 48
10.1
Processor Based Signaling ............................................................................................................ 48
10.2
Hardware Based Signaling...................................................................................................... 51
10.2.1
Receive Side .................................................................................................................. 51
10.2.2
Transmit Side................................................................................................................. 51
11
PER-CHANNEL CODE GENERATION AND LOOPBACK............................................... 52
11.1
Transmit Side Code Generation.............................................................................................. 52
11.1.1
Simple Idle Code Insertion and Per-Channel Loopback ............................................... 52
11.1.2
Per-Channel Code Insertion .......................................................................................... 53
11.2
Receive Side Code Generation ............................................................................................... 54
12
CLOCK BLOCKING REGISTERS ......................................................................................... 54
13
ELASTIC STORES OPERATION ........................................................................................... 56
13.1
Receive Side............................................................................................................................ 56
13.2
Transmit Side .......................................................................................................................... 56
14
ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .............................. 56
14.1
Hardware Scheme ................................................................................................................... 57
14.2
Internal Register Scheme Based on Double-Frame ................................................................ 57
14.3
Internal Register Scheme Based on CRC4 Multiframe .......................................................... 59
15
HDLC CONTROLLER FOR THE SA BITS OR DS0 ........................................................... 60
15.1
General Overview ................................................................................................................... 60
15.2
HDLC Status Registers ........................................................................................................... 61
15.3
Basic Operation Details .......................................................................................................... 62
15.3.1
Receive a HDLC Message............................................................................................. 62
15.3.2
Transmit an HDLC Message ......................................................................................... 62
15.4
HDLC Register Description.................................................................................................... 63
16
LINE INTERFACE FUNCTIONS............................................................................................ 68
16.1
Receive Clock and Data Recovery.......................................................................................... 69
16.2
Transmit Waveshaping and Line Driving............................................................................... 69
16.3
Jitter Attenuator....................................................................................................................... 71
16.4
Protected Interfaces................................................................................................................. 74
16.5
Receive Monitor Mode ........................................................................................................... 76
17
JTAG-VOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .................... 77
17.1
Description .............................................................................................................................. 77
17.2
TAP Controller State Machine................................................................................................78
17.3
Instruction Register ................................................................................................................. 81
17.4
Test Registers .......................................................................................................................... 83
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