參數(shù)資料
型號： DS21554LN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Interface
英文描述： DATACOM, PCM TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, LQFP-100
文件頁數(shù)： 50/117頁
文件大小： 698K
代理商： DS21554LN
DS21354 & DS21554
38 of 117
SYMBOL
POSITION NAME AND DESCRIPTION
Should be toggled after RSYSCLK has been applied and is stable. Must
be cleared and set again for a subsequent align. See Section 13 for
details.
TESA
CCR5.5
Transmit Elastic Store Align. Setting this bit from a zero to a one may
force the transmit elastic store’s write/read pointers to a minim separation
of half a frame. No action will be taken if the pointer separation is
already greater or equal to half a frame. If pointer separation is less then
half a frame, the command will be executed and data will be disrupted.
Should be toggled after TSYSCLK has been applied and is stable. Must
be cleared and set again for a subsequent align. See Section 13 for
details.
RCM4
CCR5.4
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data will appear in the RDS0M
register. See Section 9 for details.
RCM3
CCR5.3
Receive Channel Monitor Bit 3.
RCM2
CCR5.2
Receive Channel Monitor Bit 2.
RCM1
CCR5.1
Receive Channel Monitor Bit 1.
RCM0
CCR5.0
Receive Channel Monitor Bit 0. LSB of the channel decode.
CCR6: COMMON CONTROL REGISTER 6 (Address=1D Hex)
(MSB)
(LSB)
LIUODO
CDIG
LIUSI
–
TCLKSRC
RESR
TESR
SYMBOL
POSITION NAME AND DESCRIPTION
LIUODO
CCR6.7
Line Interface Open Drain Option. This control bit determines whether
the TTIP and TRING outputs will be open drain or not. The line driver
outputs can be forced open drain to allow 6Vpeak pulses to be generated
or to allow the creation of a very low power interface.
0 = allow TTIP and TRING to operate normally
1 = force the TTIP and TRING outputs to be open drain
CDIG
CCR6.6
Customer Disconnect Indication Generator. This control bit
determines whether the Line Interface will generate an unframed
...1010... pattern at TTIP and TRING instead of the normal data pattern.
0 = generate normal data at TTIP & TRING as input via TPOSI &
TNEGI
1 = generate a ...1010... pattern at TTIP and TRING
LIUSI
CCR6.5
Line Interface G.703 Synchronization Interface Enable. This control
bit determines whether the line receiver should handle a normal E1 signal
(Section 6 of G.703) or a 2.048MHz synchronization signal (Section 10
of G.703). This control has no affect on the line interface transmitter.
0 = line receiver configured to support a normal E1 signal
1 = line receiver configured to support a synchronization signal
–
CCR6.4
Not Assigned. Should be set to zero when written.
相關(guān)PDF資料
PDF描述
DS2155G DATACOM, FRAMER, PBGA100
DS21600SN PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
DS21600N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
DS2155LN DATACOM, FRAMER, PQFP100
DS21602N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21554LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2155DK 功能描述:網(wǎng)絡(luò)開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS2155G 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1/E1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2155G/T&R 制造商:Maxim Integrated Products 功能描述:DS2155 T1/E1/J1 SCT 100P CSBGA T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC LIU T1/E1/J1 SCT 100P CSBGA 制造商:Maxim Integrated Products 功能描述:Network Controller & Processor ICs T1/E1/J1 Transceiver
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