參數(shù)資料
型號: DS21554LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 100/117頁
文件大?。?/td> 698K
代理商: DS21554LN
DS21354 & DS21554
83 of 117
17.4 Test Registers
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register.
An optional test register has been included with the DS21354/554 design. This test register is the
identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is n bits in length. See Table 17-4 for all of the cell bit locations and definitions.
Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions which provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This
register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-
Reset state. See Table 17-3 and Table 17-4 for more information on bit usage.
BOUNDARY SCAN CONTROL BITS Table 17-4
BIT
PIN
SYMBOL
TYPE
CONTROL BIT DESCRIPTION
2
1
RCHBLK
O
2JTMS
I
13
8MCLK
O
4JTCLK
I
5JTRST
I
0
6
RCL
O
7JTDI
I
8N/C
9N/C
10
JTDO
O
72
11
BTS
I
71
12
LIUC
I
70
13
8XCLK
O
69
14
TEST
I
68
15
NC
16
RTIP
I
17
RRING
I
18
RVDD
19
RVSS
20
RVSS
21
MCLK
I
22
XTALD
O
67
23
NC
24
RVSS
66
25
INT
O
26
N/C
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