參數(shù)資料
型號： DS21554LN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Interface
英文描述： DATACOM, PCM TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, LQFP-100
文件頁數(shù)： 49/117頁
文件大小： 698K
代理商： DS21554LN
DS21354 & DS21554
37 of 117
SYMBOL
POSITION NAME AND DESCRIPTION
LLB
CCR4.6
Local Loopback.
0 = loopback disabled
1 = loopback enabled
LIAIS
CCR4.5
Line Interface AIS Generation Enable.
0 = allow normal data from TPOSI/TNEGI to be transmitted at TTIP and
TRING
1 = force unframed all ones to be transmitted at TTIP and TRING at the
MCLK rate
TCM4
CCR4.4
Transmit Channel Monitor Bit 4. MSB of a channel decode that
determines which transmit channel data will appear in the TDS0M
register. See Section 9 for details.
TCM3
CCR4.3
Transmit Channel Monitor Bit 3.
TCM2
CCR4.2
Transmit Channel Monitor Bit 2.
TCM1
CCR4.1
Transmit Channel Monitor Bit 1.
TCM0
CCR4.0
Transmit Channel Monitor Bit 0. LSB of the channel decode.
6.4 Remote Loopback
When CCR4.7 is set to a one, the SCT will be forced into Remote LoopBack (RLB). In this loopback,
data input via the RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO pins. Data
will continue to pass through the receive side framer of the SCT as it would normally and the data from
the transmit side formatter will be ignored. Please see Figure 3-1 for more details.
6.5 Local Loopback
When CCR4.6 is set to a one, the SCT will be forced into Local LoopBack (LLB). In this loopback, data
will continue to be transmitted as normal through the transmit side of the SCT. Data being received at
RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass
through the jitter attenuator. Please see Figure 3-1 for more details.
CCR5: COMMON CONTROL REGISTER 5 (Address=AA Hex)
(MSB)
(LSB)
LIRST
RESA
TESA
RCM4
RCM3
RCM2
RCM1
RCM0
SYMBOL
POSITION NAME AND DESCRIPTION
LIRST
CCR5.7
Line Interface Reset. Setting this bit from a zero to a one will initiate an
internal reset that affects the clock recovery state machine and jitter
attenuator. Normally this bit is only toggled on power–up. Must be
cleared and set again for a subsequent reset.
RESA
CCR5.6
Receive Elastic Store Align. Setting this bit from a zero to a one may
force the receive elastic store’s write/read pointers to a minim separation
of half a frame. No action will be taken if the pointer separation is
already greater or equal to half a frame. If pointer separation is less then
half a frame, the command will be executed and data will be disrupted.
相關(guān)PDF資料
PDF描述
DS2155G DATACOM, FRAMER, PBGA100
DS21600SN PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
DS21600N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
DS2155LN DATACOM, FRAMER, PQFP100
DS21602N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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DS2155G/T&R 制造商:Maxim Integrated Products 功能描述:DS2155 T1/E1/J1 SCT 100P CSBGA T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC LIU T1/E1/J1 SCT 100P CSBGA 制造商:Maxim Integrated Products 功能描述:Network Controller & Processor ICs T1/E1/J1 Transceiver
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