參數(shù)資料
型號： DS21554LN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Interface
英文描述： DATACOM, PCM TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, LQFP-100
文件頁數(shù)： 103/117頁
文件大小： 698K
代理商： DS21554LN
DS21354 & DS21554
86 of 117
18 INTERLEAVED PCM BUS OPERATION
In many architectures, the outputs of individual framers are combined into higher speed serial buses to
simplify transport across the system. The DS21354/554 can be configured to allow data and signaling
buses to be multiplexed into higher speed data and signaling buses eliminating external hardware saving
board space and cost.
The interleaved PCM bus option (IBO) supports two bus speeds. The 4.096 MHz bus speed allows two
SCTs to share a common bus. The 8.192 MHz bus speed allows four SCTs to share a common bus. See
Figure 18-1 for an example of 4 devices sharing a common 8.192MHz PCM bus. Each SCT that shares a
common bus must be configured through software and requires the use of one or two device pins. The
elastic stores of each SCT must be enabled and configured for 2.048 MHz operation. See Figure 18-1
and Table 18-1.
For all bus configurations, one SCT will be configured as the master device and the remaining SCTs will
be configured as slave devices. In the 4.096 MHz bus configuration there is one master and one slave. In
the 8.192 MHz bus configuration there is one master and three slaves. Refer to the IBO register
description for more detail.
IBO: INTERLEAVE BUS OPERATION REGISTER (Address = B5 Hex)
(MSB)
(LSB)
-
IBOEN
INTSEL
MSEL0
MSEL1
SYMBOL
POSITION NAME AND DESCRIPTION
-IBO.6
Not Assigned. Should be set to 0.
-IBO.6
Not Assigned. Should be set to 0.
-IBO.5
Not Assigned. Should be set to 0.
-IBO.4
Not Assigned. Should be set to 0.
IBOEN
IBO.3
Interleave Bus Operation Enable
0 = Interleave Bus Operation disabled.
1 = Interleave Bus Operation enabled.
INTSEL
IBO.2
Interleave Type Select
0 = Byte interleave.
1 = Frame interleave.
MSEL0
IBO.1
Master Device Bus Select Bit 0 See Table 18-1.
MSEL1
IBO.0
Master Device Bus Select Bit 1 See Table 18-1.
IBO MASTER DEVICE SELECT Table 18-1
MSEL1
MSEL0
Function
0
Slave device.
0
1
Master device with 1 slave device (4.096 MHz bus rate)
1
0
Master device with 3 slave devices (8.192 MHz bus rate)
11
Reserved
相關(guān)PDF資料
PDF描述
DS2155G DATACOM, FRAMER, PBGA100
DS21600SN PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
DS21600N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
DS2155LN DATACOM, FRAMER, PQFP100
DS21602N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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